0b93c4ff10d138b99abcae91139efe51fe053528
[openwrt/staging/stintel.git] / target / linux / ramips / dts / mt7620a_zyxel_keenetic-viva.dts
1 #include "mt7620a.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "zyxel,keenetic-viva", "ralink,mt7620a-soc";
8 model = "ZyXEL Keenetic Viva";
9
10 aliases {
11 led-boot = &led_power_green;
12 led-failsafe = &led_power_green;
13 led-running = &led_power_green;
14 led-upgrade = &led_power_green;
15 };
16
17 leds {
18 compatible = "gpio-leds";
19
20 wan {
21 label = "green:wan";
22 gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
23 };
24
25 usb {
26 label = "green:usb";
27 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
28 trigger-sources = <&ohci_port1>, <&ehci_port1>;
29 linux,default-trigger = "usbport";
30 };
31
32 power_alert {
33 label = "red:power";
34 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
35 };
36
37 wifi {
38 label = "green:wifi";
39 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
40 };
41
42 led_power_green: power {
43 label = "green:power";
44 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
45 };
46 };
47
48 keys {
49 compatible = "gpio-keys";
50
51 reset {
52 label = "reset";
53 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
54 linux,code = <KEY_RESTART>;
55 };
56
57 wps {
58 label = "wps";
59 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
60 linux,code = <KEY_WPS_BUTTON>;
61 };
62
63 fn {
64 label = "fn";
65 gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
66 linux,code = <BTN_0>;
67 };
68 };
69
70 gpio_export {
71 compatible = "gpio-export";
72 #size-cells = <0>;
73
74 usb_power {
75 gpio-export,name = "usb";
76 gpio-export,output = <1>;
77 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
78 };
79 };
80
81 rtl8367rb {
82 compatible = "realtek,rtl8367b";
83 cpu_port = <7>;
84 realtek,extif2 = <1 0 1 1 1 1 1 1 2>;
85 mii-bus = <&mdio0>;
86 };
87 };
88
89 &spi0 {
90 status = "okay";
91
92 flash@0 {
93 compatible = "jedec,spi-nor";
94 reg = <0>;
95 spi-max-frequency = <10000000>;
96
97 partitions {
98 compatible = "fixed-partitions";
99 #address-cells = <1>;
100 #size-cells = <1>;
101
102 partition@0 {
103 label = "u-boot";
104 reg = <0x0 0x30000>;
105 read-only;
106 };
107
108 partition@30000 {
109 label = "u-boot-env";
110 reg = <0x30000 0x10000>;
111 read-only;
112 };
113
114 factory: partition@40000 {
115 compatible = "nvmem-cells";
116 label = "factory";
117 reg = <0x40000 0x10000>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120 read-only;
121
122 eeprom_factory_0: eeprom@0 {
123 reg = <0x0 0x200>;
124 };
125
126 macaddr_factory_4: macaddr@4 {
127 reg = <0x4 0x6>;
128 };
129 };
130
131 partition@50000 {
132 compatible = "denx,uimage";
133 label = "firmware";
134 reg = <0x50000 0xfb0000>;
135 };
136 };
137 };
138 };
139
140 &state_default {
141 gpio {
142 groups = "i2c", "uartf";
143 function = "gpio";
144 };
145 };
146
147 &ethernet {
148 pinctrl-names = "default";
149 pinctrl-0 = <&rgmii2_pins &mdio_pins>;
150
151 nvmem-cells = <&macaddr_factory_4>;
152 nvmem-cell-names = "mac-address";
153
154 port@4 {
155 status = "okay";
156 mediatek,fixed-link = <1000 1 1 1>;
157 phy-mode = "rgmii";
158 phy-handle = <&phy4>;
159 };
160
161 mdio0: mdio-bus {
162 status = "okay";
163
164 phy4: ethernet-phy@4 {
165 reg = <4>;
166 phy-mode = "rgmii";
167 };
168 };
169 };
170
171 &gsw {
172 mediatek,port4-gmac;
173 mediatek,ephy-base = /bits/ 8 <8>;
174 };
175
176 &wmac {
177 nvmem-cells = <&eeprom_factory_0>;
178 nvmem-cell-names = "eeprom";
179 };
180
181 &ehci {
182 status = "okay";
183 };
184
185 &ohci {
186 status = "okay";
187 };