9ab3a70d14b3a6f24297ca80962317ea17ec5a3c
[openwrt/staging/stintel.git] / target / linux / ramips / dts / mt7620a_wavlink_wl-wn530hg4.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "wavlink,wl-wn530hg4", "ralink,mt7620a-soc";
10 model = "Wavlink WL-WN530HG4";
11
12 aliases {
13 led-boot = &led_status_blue;
14 led-failsafe = &led_status_blue;
15 led-running = &led_status_blue;
16 led-upgrade = &led_status_blue;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 led_status_blue: status_blue {
23 label = "blue:status";
24 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
25 };
26
27 status_yellow {
28 label = "yellow:status";
29 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
30 };
31
32 status_red {
33 label = "red:status";
34 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
35 };
36 };
37
38 keys {
39 compatible = "gpio-keys";
40
41 reset {
42 label = "reset";
43 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
44 linux,code = <KEY_RESTART>;
45 };
46 };
47 };
48
49 &spi0 {
50 status = "okay";
51
52 flash@0 {
53 compatible = "jedec,spi-nor";
54 reg = <0>;
55 spi-max-frequency = <24000000>;
56
57 partitions {
58 compatible = "fixed-partitions";
59 #address-cells = <1>;
60 #size-cells = <1>;
61
62 partition@0 {
63 label = "u-boot";
64 reg = <0x0 0x30000>;
65 read-only;
66 };
67
68 partition@30000 {
69 label = "config";
70 reg = <0x30000 0x10000>;
71 read-only;
72 };
73
74 factory: partition@40000 {
75 compatible = "nvmem-cells";
76 label = "factory";
77 reg = <0x40000 0x10000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 read-only;
81
82 eeprom_factory_0: eeprom@0 {
83 reg = <0x0 0x200>;
84 };
85
86 eeprom_factory_8000: eeprom@8000 {
87 reg = <0x8000 0x200>;
88 };
89
90 macaddr_factory_28: macaddr@28 {
91 reg = <0x28 0x6>;
92 };
93 };
94
95 partition@50000 {
96 compatible = "denx,uimage";
97 label = "firmware";
98 reg = <0x50000 0x7b0000>;
99 };
100 };
101 };
102 };
103
104 &state_default {
105 gpio {
106 groups = "i2c", "uartf";
107 function = "gpio";
108 };
109 };
110
111 &ethernet {
112 pinctrl-names = "default";
113 pinctrl-0 = <&rgmii2_pins &mdio_pins>;
114
115 nvmem-cells = <&macaddr_factory_28>;
116 nvmem-cell-names = "mac-address";
117
118 mediatek,portmap = "llllw";
119
120 port@5 {
121 status = "okay";
122 phy-handle = <&phy5>;
123 phy-mode = "rgmii";
124 };
125
126 mdio-bus {
127 status = "okay";
128
129 phy5: ethernet-phy@5 {
130 reg = <5>;
131 phy-mode = "rgmii";
132 };
133 };
134 };
135
136 &pcie {
137 status = "okay";
138 };
139
140 &pcie0 {
141 mt76@0,0 {
142 reg = <0x0000 0 0 0 0>;
143 nvmem-cells = <&eeprom_factory_8000>;
144 nvmem-cell-names = "eeprom";
145 ieee80211-freq-limit = <5000000 6000000>;
146 };
147 };
148
149 &wmac {
150 pinctrl-names = "default", "pa_gpio";
151 pinctrl-0 = <&pa_pins>;
152 pinctrl-1 = <&pa_gpio_pins>;
153 nvmem-cells = <&eeprom_factory_0>;
154 nvmem-cell-names = "eeprom";
155 };