target/linux/qualcommax/patches-6.6/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch

   1 From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001
   2 From: Krishna Kurapati <quic_kriskura@quicinc.com>
   3 Date: Fri, 26 Jan 2024 00:29:18 +0530
   4 Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
   5
   6 On several QUSB2 Targets, the hs_phy_irq mentioned is actually
   7 qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
   8 to qusb2_phy for such targets.
   9
  10 In actuality, the hs_phy_irq is also present in these targets, but
  11 kept in for debug purposes in hw test environments. This is not
  12 triggered by default and its functionality is mutually exclusive
  13 to that of qusb2_phy interrupt.
  14
  15 Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
  16 Add missing ss_phy_irq on some targets which allows for remote
  17 wakeup to work on a Super Speed link.
  18
  19 Also modify order of interrupts in accordance to bindings update.
  20 Since driver looks up for interrupts by name and not by index, it
  21 is safe to modify order of these interrupts in the DT.
  22
  23 Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
  24 Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
  25 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  26 ---
  27  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
  28  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
  29  arch/arm64/boot/dts/qcom/msm8953.dtsi |  7 +++++--
  30  arch/arm64/boot/dts/qcom/msm8996.dtsi |  8 ++++++--
  31  arch/arm64/boot/dts/qcom/msm8998.dtsi |  7 +++++--
  32  arch/arm64/boot/dts/qcom/sdm630.dtsi  | 17 +++++++++++++----
  33  arch/arm64/boot/dts/qcom/sm6115.dtsi  |  9 +++++++--
  34  arch/arm64/boot/dts/qcom/sm6125.dtsi  |  9 +++++++--
  35  8 files changed, 70 insertions(+), 14 deletions(-)
  36
  37 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  38 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  39 @@ -430,6 +430,12 @@
  40                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
  41                         assigned-clock-rates = <133330000>,
  42                                                <24000000>;
  43 +
  44 +                       interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
  45 +                                    <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  46 +                       interrupt-names = "pwr_event",
  47 +                                         "qusb2_phy";
  48 +
  49                         resets = <&gcc GCC_USB1_BCR>;
  50                         status = "disabled";
  51
  52 @@ -628,6 +634,13 @@
  53                                                <133330000>,
  54                                                <24000000>;
  55
  56 +                       interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
  57 +                                    <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
  58 +                                    <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
  59 +                       interrupt-names = "pwr_event",
  60 +                                         "qusb2_phy",
  61 +                                         "ss_phy_irq";
  62 +
  63                         resets = <&gcc GCC_USB0_BCR>;
  64                         status = "disabled";
  65
  66 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  67 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  68 @@ -611,6 +611,13 @@
  69                                                 <133330000>,
  70                                                 <19200000>;
  71
  72 +                       interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
  73 +                                    <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
  74 +                                    <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
  75 +                       interrupt-names = "pwr_event",
  76 +                                         "qusb2_phy",
  77 +                                         "ss_phy_irq";
  78 +
  79                         power-domains = <&gcc USB0_GDSC>;
  80
  81                         resets = <&gcc GCC_USB0_BCR>;
  82 @@ -653,6 +660,13 @@
  83                                                 <133330000>,
  84                                                 <19200000>;
  85
  86 +                       interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
  87 +                                    <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
  88 +                                    <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
  89 +                       interrupt-names = "pwr_event",
  90 +                                         "qusb2_phy",
  91 +                                         "ss_phy_irq";
  92 +
  93                         power-domains = <&gcc USB1_GDSC>;
  94
  95                         resets = <&gcc GCC_USB1_BCR>;