target/linux/qualcommax/patches-6.6/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch

   1 From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001
   2 From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
   3 Date: Thu, 14 Sep 2023 12:29:59 +0530
   4 Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
   5  provider for mailbox
   6
   7 While the kernel is booting up, APSS clock / CPU clock will be running
   8 at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
   9 APSS PLL will be configured to the rate based on the opp table and the
  10 source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
  11 consume the GPLL0, with this inclusion, CPU Freq correctly reports that
  12 CPU is running at 800MHz rather than 24MHz.
  13
  14 Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
  15 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  16 Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com
  17 [bjorn: Updated commit message, as requested by Kathiravan]
  18 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  19 ---
  20  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
  21  1 file changed, 2 insertions(+), 2 deletions(-)
  22
  23 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  24 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  25 @@ -618,8 +618,8 @@
  26                         compatible = "qcom,ipq6018-apcs-apps-global";
  27                         reg = <0x0 0x0b111000 0x0 0x1000>;
  28                         #clock-cells = <1>;
  29 -                       clocks = <&a53pll>, <&xo>;
  30 -                       clock-names = "pll", "xo";
  31 +                       clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
  32 +                       clock-names = "pll", "xo", "gpll0";
  33                         #mbox-cells = <1>;
  34                 };
  35