target/linux/qualcommax/patches-6.1/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch

   1 From 0c5b5243ad55ae744e790ba90c5ad37a93bd1377 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Tue, 11 Oct 2022 23:38:45 +0200
   4 Subject: [PATCH] clk: qcom: ipq6018: workaround networking clock parenting
   5
   6 Currently, networking clocks are only looked up by fw_name however,
   7 these are registered and setup by SSDK and are not available to the
   8 GCC driver at all, so work around that by providing a global name
   9 fallback.
  10
  11 While we are here, provide global fallback for bias_pll_cc_clk and
  12 bias_pll_nss_noc_clk as well as these are fixed clocks also not available
  13 to the driver.
  14
  15 Signed-off-by: Robert Marko <robimarko@gmail.com>
  16 ---
  17  drivers/clk/qcom/gcc-ipq6018.c | 39 +++++++++++++++++-----------------
  18  1 file changed, 19 insertions(+), 20 deletions(-)
  19
  20 --- a/drivers/clk/qcom/gcc-ipq6018.c
  21 +++ b/drivers/clk/qcom/gcc-ipq6018.c
  22 @@ -361,7 +361,7 @@ static const struct freq_tbl ftbl_nss_pp
  23
  24  static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
  25         { .fw_name = "xo" },
  26 -       { .fw_name = "bias_pll_cc_clk" },
  27 +       { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
  28         { .hw = &gpll0.clkr.hw },
  29         { .hw = &gpll4.clkr.hw },
  30         { .hw = &nss_crypto_pll.clkr.hw },
  31 @@ -527,12 +527,12 @@ static const struct freq_tbl ftbl_nss_po
  32  static const struct clk_parent_data
  33  gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
  34         { .fw_name = "xo" },
  35 -       { .fw_name = "uniphy0_gcc_rx_clk" },
  36 -       { .fw_name = "uniphy0_gcc_tx_clk" },
  37 -       { .fw_name = "uniphy1_gcc_rx_clk" },
  38 -       { .fw_name = "uniphy1_gcc_tx_clk" },
  39 +       { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
  40 +       { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
  41 +       { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
  42 +       { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
  43         { .hw = &ubi32_pll.clkr.hw },
  44 -       { .fw_name = "bias_pll_cc_clk" },
  45 +       { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
  46  };
  47
  48  static const struct parent_map
  49 @@ -574,12 +574,12 @@ static const struct freq_tbl ftbl_nss_po
  50  static const struct clk_parent_data
  51  gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
  52         { .fw_name = "xo" },
  53 -       { .fw_name = "uniphy0_gcc_tx_clk" },
  54 -       { .fw_name = "uniphy0_gcc_rx_clk" },
  55 -       { .fw_name = "uniphy1_gcc_tx_clk" },
  56 -       { .fw_name = "uniphy1_gcc_rx_clk" },
  57 +       { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
  58 +       { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
  59 +       { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
  60 +       { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
  61         { .hw = &ubi32_pll.clkr.hw },
  62 -       { .fw_name = "bias_pll_cc_clk" },
  63 +       { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
  64  };
  65
  66  static const struct parent_map
  67 @@ -715,10 +715,10 @@ static const struct freq_tbl ftbl_nss_po
  68
  69  static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
  70         { .fw_name = "xo" },
  71 -       { .fw_name = "uniphy0_gcc_rx_clk" },
  72 -       { .fw_name = "uniphy0_gcc_tx_clk" },
  73 +       { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
  74 +       { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
  75         { .hw = &ubi32_pll.clkr.hw },
  76 -       { .fw_name = "bias_pll_cc_clk" },
  77 +       { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
  78  };
  79
  80  static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
  81 @@ -751,10 +751,10 @@ static const struct freq_tbl ftbl_nss_po
  82
  83  static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
  84         { .fw_name = "xo" },
  85 -       { .fw_name = "uniphy0_gcc_tx_clk" },
  86 -       { .fw_name = "uniphy0_gcc_rx_clk" },
  87 +       { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
  88 +       { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
  89         { .hw = &ubi32_pll.clkr.hw },
  90 -       { .fw_name = "bias_pll_cc_clk" },
  91 +       { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
  92  };
  93
  94  static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
  95 @@ -1898,12 +1898,11 @@ static const struct freq_tbl ftbl_ubi32_
  96         { }
  97  };
  98
  99 -static const struct clk_parent_data
 100 -                       gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
 101 +static const struct clk_parent_data gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
 102         { .fw_name = "xo" },
 103         { .hw = &gpll0.clkr.hw },
 104         { .hw = &gpll2.clkr.hw },
 105 -       { .fw_name = "bias_pll_nss_noc_clk" },
 106 +       { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
 107  };
 108
 109  static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {