target/linux/qualcommax/patches-6.1/0900-power-Add-Qualcomm-APM.patch

   1 From 6c98adf98236b8644b8f5e1aa7af9f1a88ea2766 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Mon, 11 Apr 2022 14:38:08 +0200
   4 Subject: [PATCH] power: Add Qualcomm APM
   5
   6 Add Qualcomm APM driver, which allows scaling cache and memory fabrics.
   7
   8 Signed-off-by: Robert Marko <robimarko@gmail.com>
   9 ---
  10  drivers/power/Kconfig          |   1 +
  11  drivers/power/Makefile         |   1 +
  12  drivers/power/qcom/Kconfig     |   7 +
  13  drivers/power/qcom/Makefile    |   1 +
  14  drivers/power/qcom/apm.c       | 944 +++++++++++++++++++++++++++++++++
  15  include/linux/power/qcom/apm.h |  48 ++
  16  6 files changed, 1002 insertions(+)
  17  create mode 100644 drivers/power/qcom/Kconfig
  18  create mode 100644 drivers/power/qcom/Makefile
  19  create mode 100644 drivers/power/qcom/apm.c
  20  create mode 100644 include/linux/power/qcom/apm.h
  21
  22 --- a/drivers/power/Kconfig
  23 +++ b/drivers/power/Kconfig
  24 @@ -1,3 +1,4 @@
  25  # SPDX-License-Identifier: GPL-2.0-only
  26  source "drivers/power/reset/Kconfig"
  27  source "drivers/power/supply/Kconfig"
  28 +source "drivers/power/qcom/Kconfig"
  29 --- a/drivers/power/Makefile
  30 +++ b/drivers/power/Makefile
  31 @@ -1,3 +1,4 @@
  32  # SPDX-License-Identifier: GPL-2.0-only
  33  obj-$(CONFIG_POWER_RESET)      += reset/
  34  obj-$(CONFIG_POWER_SUPPLY)     += supply/
  35 +obj-$(CONFIG_QCOM_APM)         += qcom/
  36 --- /dev/null
  37 +++ b/drivers/power/qcom/Kconfig
  38 @@ -0,0 +1,7 @@
  39 +config QCOM_APM
  40 +       bool "Qualcomm Technologies Inc platform specific APM driver"
  41 +       help
  42 +       Platform specific driver to manage the power source of
  43 +       memory arrays. Interfaces with regulator drivers to ensure
  44 +       SRAM Vmin requirements are met across different performance
  45 +       levels.
  46 --- /dev/null
  47 +++ b/drivers/power/qcom/Makefile
  48 @@ -0,0 +1 @@
  49 +obj-$(CONFIG_QCOM_APM)         += apm.o
  50 --- /dev/null
  51 +++ b/drivers/power/qcom/apm.c
  52 @@ -0,0 +1,944 @@
  53 +/*
  54 + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
  55 + *
  56 + * This program is free software; you can redistribute it and/or modify
  57 + * it under the terms of the GNU General Public License version 2 and
  58 + * only version 2 as published by the Free Software Foundation.
  59 + *
  60 + * This program is distributed in the hope that it will be useful,
  61 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  62 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  63 + * GNU General Public License for more details.
  64 + */
  65 +
  66 +#define pr_fmt(fmt) "%s: " fmt, __func__
  67 +
  68 +#include <linux/debugfs.h>
  69 +#include <linux/delay.h>
  70 +#include <linux/of_device.h>
  71 +#include <linux/init.h>
  72 +#include <linux/io.h>
  73 +#include <linux/kernel.h>
  74 +#include <linux/list.h>
  75 +#include <linux/module.h>
  76 +#include <linux/of.h>
  77 +#include <linux/platform_device.h>
  78 +#include <linux/slab.h>
  79 +#include <linux/string.h>
  80 +#include <linux/power/qcom/apm.h>
  81 +
  82 +/*
  83 + *        VDD_APCC
  84 + * =============================================================
  85 + *       |      VDD_MX                  |                    |
  86 + *       |    ==========================|=============       |
  87 + *    ___|___   ___|___    ___|___   ___|___    ___|___   ___|___
  88 + *   |       | |       |  |       | |       |  |       | |       |
  89 + *   | APCC  | | MX HS |  | MX HS | | APCC  |  | MX HS | | APCC  |
  90 + *   |  HS   | |       |  |       | |  HS   |  |       | |  HS   |
  91 + *   |_______| |_______|  |_______| |_______|  |_______| |_______|
  92 + *       |_________|          |_________|         |__________|
  93 + *            |                    |                    |
  94 + *      ______|_____         ______|_____        _______|_____
  95 + *     |            |       |            |      |             |
  96 + *     |            |       |            |      |             |
  97 + *     |  CPU MEM   |       |   L2 MEM   |      |    L3 MEM   |
  98 + *     |   Arrays   |       |   Arrays   |      |    Arrays   |
  99 + *     |            |       |            |      |             |
 100 + *     |____________|       |____________|      |_____________|
 101 + *
 102 + */
 103 +
 104 +/* Register value definitions */
 105 +#define APCS_GFMUXA_SEL_VAL            0x13
 106 +#define APCS_GFMUXA_DESEL_VAL          0x03
 107 +#define MSM_APM_MX_MODE_VAL            0x00
 108 +#define MSM_APM_APCC_MODE_VAL          0x10
 109 +#define MSM_APM_MX_DONE_VAL            0x00
 110 +#define MSM_APM_APCC_DONE_VAL          0x03
 111 +#define MSM_APM_OVERRIDE_SEL_VAL       0xb0
 112 +#define MSM_APM_SEC_CLK_SEL_VAL        0x30
 113 +#define SPM_EVENT_SET_VAL              0x01
 114 +#define SPM_EVENT_CLEAR_VAL            0x00
 115 +
 116 +/* Register bit mask definitions */
 117 +#define MSM_APM_CTL_STS_MASK            0x0f
 118 +
 119 +/* Register offset definitions */
 120 +#define APCC_APM_MODE              0x00000098
 121 +#define APCC_APM_CTL_STS           0x000000a8
 122 +#define APCS_SPARE                 0x00000068
 123 +#define APCS_VERSION               0x00000fd0
 124 +
 125 +#define HMSS_VERSION_1P2           0x10020000
 126 +
 127 +#define MSM_APM_SWITCH_TIMEOUT_US  10
 128 +#define SPM_WAKEUP_DELAY_US        2
 129 +#define SPM_EVENT_NUM              6
 130 +
 131 +#define MSM_APM_DRIVER_NAME        "qcom,msm-apm"
 132 +
 133 +enum {
 134 +       MSM8996_ID,
 135 +       MSM8953_ID,
 136 +       IPQ807x_ID,
 137 +};
 138 +
 139 +struct msm_apm_ctrl_dev {
 140 +       struct list_head        list;
 141 +       struct device           *dev;
 142 +       enum msm_apm_supply     supply;
 143 +       spinlock_t              lock;
 144 +       void __iomem            *reg_base;
 145 +       void __iomem            *apcs_csr_base;
 146 +       void __iomem            **apcs_spm_events_addr;
 147 +       void __iomem            *apc0_pll_ctl_addr;
 148 +       void __iomem            *apc1_pll_ctl_addr;
 149 +       u32                     version;
 150 +       struct dentry           *debugfs;
 151 +       u32                     msm_id;
 152 +};
 153 +
 154 +#if defined(CONFIG_DEBUG_FS)
 155 +static struct dentry *apm_debugfs_base;
 156 +#endif
 157 +
 158 +static DEFINE_MUTEX(apm_ctrl_list_mutex);
 159 +static LIST_HEAD(apm_ctrl_list);
 160 +
 161 +/*
 162 + * Get the resources associated with the APM controller from device tree
 163 + * and remap all I/O addresses that are relevant to this HW revision.
 164 + */
 165 +static int msm_apm_ctrl_devm_ioremap(struct platform_device *pdev,
 166 +                                    struct msm_apm_ctrl_dev *ctrl)
 167 +{
 168 +       struct device *dev = &pdev->dev;
 169 +       struct resource *res;
 170 +       static const char *res_name[SPM_EVENT_NUM] = {
 171 +               "apc0-l2-spm",
 172 +               "apc1-l2-spm",
 173 +               "apc0-cpu0-spm",
 174 +               "apc0-cpu1-spm",
 175 +               "apc1-cpu0-spm",
 176 +               "apc1-cpu1-spm"
 177 +       };
 178 +       int i, ret = 0;
 179 +
 180 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
 181 +       if (!res) {
 182 +               dev_err(dev, "Missing PM APCC Global register physical address");
 183 +               return -EINVAL;
 184 +       }
 185 +       ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
 186 +       if (!ctrl->reg_base) {
 187 +               dev_err(dev, "Failed to map PM APCC Global registers\n");
 188 +               return -ENOMEM;
 189 +       }
 190 +
 191 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs-csr");
 192 +       if (!res) {
 193 +               dev_err(dev, "Missing APCS CSR physical base address");
 194 +               return -EINVAL;
 195 +       }
 196 +       ctrl->apcs_csr_base = devm_ioremap(dev, res->start, resource_size(res));
 197 +       if (!ctrl->apcs_csr_base) {
 198 +               dev_err(dev, "Failed to map APCS CSR registers\n");
 199 +               return -ENOMEM;
 200 +       }
 201 +
 202 +       ctrl->version = readl_relaxed(ctrl->apcs_csr_base + APCS_VERSION);
 203 +
 204 +       if (ctrl->version >= HMSS_VERSION_1P2)
 205 +               return ret;
 206 +
 207 +       ctrl->apcs_spm_events_addr = devm_kzalloc(&pdev->dev,
 208 +                                                 SPM_EVENT_NUM
 209 +                                                 * sizeof(void __iomem *),
 210 +                                                 GFP_KERNEL);
 211 +       if (!ctrl->apcs_spm_events_addr) {
 212 +               dev_err(dev, "Failed to allocate memory for APCS SPM event registers\n");
 213 +               return -ENOMEM;
 214 +       }
 215 +
 216 +       for (i = 0; i < SPM_EVENT_NUM; i++) {
 217 +               res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 218 +                                                  res_name[i]);
 219 +               if (!res) {
 220 +                       dev_err(dev, "Missing address for %s\n", res_name[i]);
 221 +                       ret = -EINVAL;
 222 +                       goto free_events;
 223 +               }
 224 +
 225 +               ctrl->apcs_spm_events_addr[i] = devm_ioremap(dev, res->start,
 226 +                                               resource_size(res));
 227 +               if (!ctrl->apcs_spm_events_addr[i]) {
 228 +                       dev_err(dev, "Failed to map %s\n", res_name[i]);
 229 +                       ret = -ENOMEM;
 230 +                       goto free_events;
 231 +               }
 232 +
 233 +               dev_dbg(dev, "%s event phys: %pa virt:0x%p\n", res_name[i],
 234 +                       &res->start, ctrl->apcs_spm_events_addr[i]);
 235 +       }
 236 +
 237 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 238 +                                          "apc0-pll-ctl");
 239 +       if (!res) {
 240 +               dev_err(dev, "Missing APC0 PLL CTL physical address\n");
 241 +               ret = -EINVAL;
 242 +               goto free_events;
 243 +       }
 244 +
 245 +       ctrl->apc0_pll_ctl_addr = devm_ioremap(dev,
 246 +                                          res->start,
 247 +                                          resource_size(res));
 248 +       if (!ctrl->apc0_pll_ctl_addr) {
 249 +               dev_err(dev, "Failed to map APC0 PLL CTL register\n");
 250 +               ret = -ENOMEM;
 251 +               goto free_events;
 252 +       }
 253 +
 254 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 255 +                                          "apc1-pll-ctl");
 256 +       if (!res) {
 257 +               dev_err(dev, "Missing APC1 PLL CTL physical address\n");
 258 +               ret = -EINVAL;
 259 +               goto free_events;
 260 +       }
 261 +
 262 +       ctrl->apc1_pll_ctl_addr = devm_ioremap(dev,
 263 +                                          res->start,
 264 +                                          resource_size(res));
 265 +       if (!ctrl->apc1_pll_ctl_addr) {
 266 +               dev_err(dev, "Failed to map APC1 PLL CTL register\n");
 267 +               ret = -ENOMEM;
 268 +               goto free_events;
 269 +       }
 270 +
 271 +       return ret;
 272 +
 273 +free_events:
 274 +       devm_kfree(dev, ctrl->apcs_spm_events_addr);
 275 +       return ret;
 276 +}
 277 +
 278 +/* 8953 register offset definition */
 279 +#define MSM8953_APM_DLY_CNTR   0x2ac
 280 +
 281 +/* Register field shift definitions */
 282 +#define APM_CTL_SEL_SWITCH_DLY_SHIFT   0
 283 +#define APM_CTL_RESUME_CLK_DLY_SHIFT   8
 284 +#define APM_CTL_HALT_CLK_DLY_SHIFT     16
 285 +#define APM_CTL_POST_HALT_DLY_SHIFT    24
 286 +
 287 +/* Register field mask definitions */
 288 +#define APM_CTL_SEL_SWITCH_DLY_MASK    GENMASK(7, 0)
 289 +#define APM_CTL_RESUME_CLK_DLY_MASK    GENMASK(15, 8)
 290 +#define APM_CTL_HALT_CLK_DLY_MASK      GENMASK(23, 16)
 291 +#define APM_CTL_POST_HALT_DLY_MASK     GENMASK(31, 24)
 292 +
 293 +/*
 294 + * Get the resources associated with the msm8953 APM controller from
 295 + * device tree, remap all I/O addresses, and program the initial
 296 + * register configuration required for the 8953 APM controller device.
 297 + */
 298 +static int msm8953_apm_ctrl_init(struct platform_device *pdev,
 299 +                                    struct msm_apm_ctrl_dev *ctrl)
 300 +{
 301 +       struct device *dev = &pdev->dev;
 302 +       struct resource *res;
 303 +       u32 delay_counter, val = 0, regval = 0;
 304 +       int rc = 0;
 305 +
 306 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
 307 +       if (!res) {
 308 +               dev_err(dev, "Missing PM APCC Global register physical address\n");
 309 +               return -ENODEV;
 310 +       }
 311 +       ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
 312 +       if (!ctrl->reg_base) {
 313 +               dev_err(dev, "Failed to map PM APCC Global registers\n");
 314 +               return -ENOMEM;
 315 +       }
 316 +
 317 +       /*
 318 +        * Initial APM register configuration required before starting
 319 +        * APM HW controller.
 320 +        */
 321 +       regval = readl_relaxed(ctrl->reg_base + MSM8953_APM_DLY_CNTR);
 322 +       val = regval;
 323 +
 324 +       if (of_find_property(dev->of_node, "qcom,apm-post-halt-delay", NULL)) {
 325 +               rc = of_property_read_u32(dev->of_node,
 326 +                               "qcom,apm-post-halt-delay", &delay_counter);
 327 +               if (rc < 0) {
 328 +                       dev_err(dev, "apm-post-halt-delay read failed, rc = %d",
 329 +                               rc);
 330 +                       return rc;
 331 +               }
 332 +
 333 +               val &= ~APM_CTL_POST_HALT_DLY_MASK;
 334 +               val |= (delay_counter << APM_CTL_POST_HALT_DLY_SHIFT)
 335 +                       & APM_CTL_POST_HALT_DLY_MASK;
 336 +       }
 337 +
 338 +       if (of_find_property(dev->of_node, "qcom,apm-halt-clk-delay", NULL)) {
 339 +               rc = of_property_read_u32(dev->of_node,
 340 +                               "qcom,apm-halt-clk-delay", &delay_counter);
 341 +               if (rc < 0) {
 342 +                       dev_err(dev, "apm-halt-clk-delay read failed, rc = %d",
 343 +                               rc);
 344 +                       return rc;
 345 +               }
 346 +
 347 +               val &= ~APM_CTL_HALT_CLK_DLY_MASK;
 348 +               val |= (delay_counter << APM_CTL_HALT_CLK_DLY_SHIFT)
 349 +                       & APM_CTL_HALT_CLK_DLY_MASK;
 350 +       }
 351 +
 352 +       if (of_find_property(dev->of_node, "qcom,apm-resume-clk-delay", NULL)) {
 353 +               rc = of_property_read_u32(dev->of_node,
 354 +                               "qcom,apm-resume-clk-delay", &delay_counter);
 355 +               if (rc < 0) {
 356 +                       dev_err(dev, "apm-resume-clk-delay read failed, rc = %d",
 357 +                               rc);
 358 +                       return rc;
 359 +               }
 360 +
 361 +               val &= ~APM_CTL_RESUME_CLK_DLY_MASK;
 362 +               val |= (delay_counter << APM_CTL_RESUME_CLK_DLY_SHIFT)
 363 +                       & APM_CTL_RESUME_CLK_DLY_MASK;
 364 +       }
 365 +
 366 +       if (of_find_property(dev->of_node, "qcom,apm-sel-switch-delay", NULL)) {
 367 +               rc = of_property_read_u32(dev->of_node,
 368 +                               "qcom,apm-sel-switch-delay", &delay_counter);
 369 +               if (rc < 0) {
 370 +                       dev_err(dev, "apm-sel-switch-delay read failed, rc = %d",
 371 +                               rc);
 372 +                       return rc;
 373 +               }
 374 +
 375 +               val &= ~APM_CTL_SEL_SWITCH_DLY_MASK;
 376 +               val |= (delay_counter << APM_CTL_SEL_SWITCH_DLY_SHIFT)
 377 +                       & APM_CTL_SEL_SWITCH_DLY_MASK;
 378 +       }
 379 +
 380 +       if (val != regval) {
 381 +               writel_relaxed(val, ctrl->reg_base + MSM8953_APM_DLY_CNTR);
 382 +               /* make sure write completes before return */
 383 +               mb();
 384 +       }
 385 +
 386 +       return rc;
 387 +}
 388 +
 389 +static int msm8996_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
 390 +{
 391 +       int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
 392 +       u32 regval;
 393 +       int ret = 0;
 394 +       unsigned long flags;
 395 +
 396 +       spin_lock_irqsave(&ctrl_dev->lock, flags);
 397 +
 398 +       /* Perform revision-specific programming steps */
 399 +       if (ctrl_dev->version < HMSS_VERSION_1P2) {
 400 +               /* Clear SPM events */
 401 +               for (i = 0; i < SPM_EVENT_NUM; i++)
 402 +                       writel_relaxed(SPM_EVENT_CLEAR_VAL,
 403 +                                      ctrl_dev->apcs_spm_events_addr[i]);
 404 +
 405 +               udelay(SPM_WAKEUP_DELAY_US);
 406 +
 407 +               /* Switch APC/CBF to GPLL0 clock */
 408 +               writel_relaxed(APCS_GFMUXA_SEL_VAL,
 409 +                              ctrl_dev->apcs_csr_base + APCS_SPARE);
 410 +               ndelay(200);
 411 +               writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
 412 +                              ctrl_dev->apc0_pll_ctl_addr);
 413 +               ndelay(200);
 414 +               writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
 415 +                              ctrl_dev->apc1_pll_ctl_addr);
 416 +
 417 +               /* Ensure writes complete before proceeding */
 418 +               mb();
 419 +       }
 420 +
 421 +       /* Switch arrays to MX supply and wait for its completion */
 422 +       writel_relaxed(MSM_APM_MX_MODE_VAL, ctrl_dev->reg_base +
 423 +                      APCC_APM_MODE);
 424 +
 425 +       /* Ensure write above completes before delaying */
 426 +       mb();
 427 +
 428 +       while (timeout > 0) {
 429 +               regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
 430 +               if ((regval & MSM_APM_CTL_STS_MASK) ==
 431 +                   MSM_APM_MX_DONE_VAL)
 432 +                       break;
 433 +
 434 +               udelay(1);
 435 +               timeout--;
 436 +       }
 437 +
 438 +       if (timeout == 0) {
 439 +               ret = -ETIMEDOUT;
 440 +               dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
 441 +                       regval);
 442 +       }
 443 +
 444 +       /* Perform revision-specific programming steps */
 445 +       if (ctrl_dev->version < HMSS_VERSION_1P2) {
 446 +               /* Switch APC/CBF clocks to original source */
 447 +               writel_relaxed(APCS_GFMUXA_DESEL_VAL,
 448 +                              ctrl_dev->apcs_csr_base + APCS_SPARE);
 449 +               ndelay(200);
 450 +               writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
 451 +                              ctrl_dev->apc0_pll_ctl_addr);
 452 +               ndelay(200);
 453 +               writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
 454 +                              ctrl_dev->apc1_pll_ctl_addr);
 455 +
 456 +               /* Complete clock source switch before SPM event sequence */
 457 +               mb();
 458 +
 459 +               /* Set SPM events */
 460 +               for (i = 0; i < SPM_EVENT_NUM; i++)
 461 +                       writel_relaxed(SPM_EVENT_SET_VAL,
 462 +                                      ctrl_dev->apcs_spm_events_addr[i]);
 463 +       }
 464 +
 465 +       if (!ret) {
 466 +               ctrl_dev->supply = MSM_APM_SUPPLY_MX;
 467 +               dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
 468 +       }
 469 +
 470 +       spin_unlock_irqrestore(&ctrl_dev->lock, flags);
 471 +
 472 +       return ret;
 473 +}
 474 +
 475 +static int msm8996_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
 476 +{
 477 +       int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
 478 +       u32 regval;
 479 +       int ret = 0;
 480 +       unsigned long flags;
 481 +
 482 +       spin_lock_irqsave(&ctrl_dev->lock, flags);
 483 +
 484 +       /* Perform revision-specific programming steps */
 485 +       if (ctrl_dev->version < HMSS_VERSION_1P2) {
 486 +               /* Clear SPM events */
 487 +               for (i = 0; i < SPM_EVENT_NUM; i++)
 488 +                       writel_relaxed(SPM_EVENT_CLEAR_VAL,
 489 +                                      ctrl_dev->apcs_spm_events_addr[i]);
 490 +
 491 +               udelay(SPM_WAKEUP_DELAY_US);
 492 +
 493 +               /* Switch APC/CBF to GPLL0 clock */
 494 +               writel_relaxed(APCS_GFMUXA_SEL_VAL,
 495 +                              ctrl_dev->apcs_csr_base + APCS_SPARE);
 496 +               ndelay(200);
 497 +               writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
 498 +                              ctrl_dev->apc0_pll_ctl_addr);
 499 +               ndelay(200);
 500 +               writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
 501 +                              ctrl_dev->apc1_pll_ctl_addr);
 502 +
 503 +               /* Ensure previous writes complete before proceeding */
 504 +               mb();
 505 +       }
 506 +
 507 +       /* Switch arrays to APCC supply and wait for its completion */
 508 +       writel_relaxed(MSM_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
 509 +                      APCC_APM_MODE);
 510 +
 511 +       /* Ensure write above completes before delaying */
 512 +       mb();
 513 +
 514 +       while (timeout > 0) {
 515 +               regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
 516 +               if ((regval & MSM_APM_CTL_STS_MASK) ==
 517 +                   MSM_APM_APCC_DONE_VAL)
 518 +                       break;
 519 +
 520 +               udelay(1);
 521 +               timeout--;
 522 +       }
 523 +
 524 +       if (timeout == 0) {
 525 +               ret = -ETIMEDOUT;
 526 +               dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
 527 +                       regval);
 528 +       }
 529 +
 530 +       /* Perform revision-specific programming steps */
 531 +       if (ctrl_dev->version < HMSS_VERSION_1P2) {
 532 +               /* Set SPM events */
 533 +               for (i = 0; i < SPM_EVENT_NUM; i++)
 534 +                       writel_relaxed(SPM_EVENT_SET_VAL,
 535 +                                      ctrl_dev->apcs_spm_events_addr[i]);
 536 +
 537 +               /* Complete SPM event sequence before clock source switch */
 538 +               mb();
 539 +
 540 +               /* Switch APC/CBF clocks to original source */
 541 +               writel_relaxed(APCS_GFMUXA_DESEL_VAL,
 542 +                              ctrl_dev->apcs_csr_base + APCS_SPARE);
 543 +               ndelay(200);
 544 +               writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
 545 +                              ctrl_dev->apc0_pll_ctl_addr);
 546 +               ndelay(200);
 547 +               writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
 548 +                              ctrl_dev->apc1_pll_ctl_addr);
 549 +       }
 550 +
 551 +       if (!ret) {
 552 +               ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
 553 +               dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
 554 +       }
 555 +
 556 +       spin_unlock_irqrestore(&ctrl_dev->lock, flags);
 557 +
 558 +       return ret;
 559 +}
 560 +
 561 +/* 8953 register value definitions */
 562 +#define MSM8953_APM_MX_MODE_VAL            0x00
 563 +#define MSM8953_APM_APCC_MODE_VAL          0x02
 564 +#define MSM8953_APM_MX_DONE_VAL            0x00
 565 +#define MSM8953_APM_APCC_DONE_VAL          0x03
 566 +
 567 +/* 8953 register offset definitions */
 568 +#define MSM8953_APCC_APM_MODE              0x000002a8
 569 +#define MSM8953_APCC_APM_CTL_STS           0x000002b0
 570 +
 571 +/* 8953 constants */
 572 +#define MSM8953_APM_SWITCH_TIMEOUT_US      500
 573 +
 574 +/* Register bit mask definitions */
 575 +#define MSM8953_APM_CTL_STS_MASK           0x1f
 576 +
 577 +static int msm8953_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
 578 +{
 579 +       int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
 580 +       u32 regval;
 581 +       int ret = 0;
 582 +       unsigned long flags;
 583 +
 584 +       spin_lock_irqsave(&ctrl_dev->lock, flags);
 585 +
 586 +       /* Switch arrays to MX supply and wait for its completion */
 587 +       writel_relaxed(MSM8953_APM_MX_MODE_VAL, ctrl_dev->reg_base +
 588 +                      MSM8953_APCC_APM_MODE);
 589 +
 590 +       /* Ensure write above completes before delaying */
 591 +       mb();
 592 +
 593 +       while (timeout > 0) {
 594 +               regval = readl_relaxed(ctrl_dev->reg_base +
 595 +                                       MSM8953_APCC_APM_CTL_STS);
 596 +               if ((regval & MSM8953_APM_CTL_STS_MASK) ==
 597 +                               MSM8953_APM_MX_DONE_VAL)
 598 +                       break;
 599 +
 600 +               udelay(1);
 601 +               timeout--;
 602 +       }
 603 +
 604 +       if (timeout == 0) {
 605 +               ret = -ETIMEDOUT;
 606 +               dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
 607 +                       regval);
 608 +       } else {
 609 +               ctrl_dev->supply = MSM_APM_SUPPLY_MX;
 610 +               dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
 611 +       }
 612 +
 613 +       spin_unlock_irqrestore(&ctrl_dev->lock, flags);
 614 +
 615 +       return ret;
 616 +}
 617 +
 618 +static int msm8953_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
 619 +{
 620 +       int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
 621 +       u32 regval;
 622 +       int ret = 0;
 623 +       unsigned long flags;
 624 +
 625 +       spin_lock_irqsave(&ctrl_dev->lock, flags);
 626 +
 627 +       /* Switch arrays to APCC supply and wait for its completion */
 628 +       writel_relaxed(MSM8953_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
 629 +                      MSM8953_APCC_APM_MODE);
 630 +
 631 +       /* Ensure write above completes before delaying */
 632 +       mb();
 633 +
 634 +       while (timeout > 0) {
 635 +               regval = readl_relaxed(ctrl_dev->reg_base +
 636 +                                       MSM8953_APCC_APM_CTL_STS);
 637 +               if ((regval & MSM8953_APM_CTL_STS_MASK) ==
 638 +                               MSM8953_APM_APCC_DONE_VAL)
 639 +                       break;
 640 +
 641 +               udelay(1);
 642 +               timeout--;
 643 +       }
 644 +
 645 +       if (timeout == 0) {
 646 +               ret = -ETIMEDOUT;
 647 +               dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
 648 +                       regval);
 649 +       } else {
 650 +               ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
 651 +               dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
 652 +       }
 653 +
 654 +       spin_unlock_irqrestore(&ctrl_dev->lock, flags);
 655 +
 656 +       return ret;
 657 +}
 658 +
 659 +static int msm_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
 660 +{
 661 +       int ret = 0;
 662 +
 663 +       switch (ctrl_dev->msm_id) {
 664 +       case MSM8996_ID:
 665 +               ret = msm8996_apm_switch_to_mx(ctrl_dev);
 666 +               break;
 667 +       case MSM8953_ID:
 668 +       case IPQ807x_ID:
 669 +               ret = msm8953_apm_switch_to_mx(ctrl_dev);
 670 +               break;
 671 +       }
 672 +
 673 +       return ret;
 674 +}
 675 +
 676 +static int msm_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
 677 +{
 678 +       int ret = 0;
 679 +
 680 +       switch (ctrl_dev->msm_id) {
 681 +       case MSM8996_ID:
 682 +               ret = msm8996_apm_switch_to_apcc(ctrl_dev);
 683 +               break;
 684 +       case MSM8953_ID:
 685 +       case IPQ807x_ID:
 686 +               ret = msm8953_apm_switch_to_apcc(ctrl_dev);
 687 +               break;
 688 +       }
 689 +
 690 +       return ret;
 691 +}
 692 +
 693 +/**
 694 + * msm_apm_get_supply() - Returns the supply that is currently
 695 + *                     powering the memory arrays
 696 + * @ctrl_dev:                   Pointer to an MSM APM controller device
 697 + *
 698 + * Returns the supply currently selected by the APM.
 699 + */
 700 +int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
 701 +{
 702 +       return ctrl_dev->supply;
 703 +}
 704 +EXPORT_SYMBOL(msm_apm_get_supply);
 705 +
 706 +/**
 707 + * msm_apm_set_supply() - Perform the necessary steps to switch the voltage
 708 + *                        source of the memory arrays to a given supply
 709 + * @ctrl_dev:                   Pointer to an MSM APM controller device
 710 + * @supply:                     Power rail to use as supply for the memory
 711 + *                              arrays
 712 + *
 713 + * Returns 0 on success, -ETIMEDOUT on APM switch timeout, or -EPERM if
 714 + * the supply is not supported.
 715 + */
 716 +int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
 717 +                      enum msm_apm_supply supply)
 718 +{
 719 +       int ret;
 720 +
 721 +       switch (supply) {
 722 +       case MSM_APM_SUPPLY_APCC:
 723 +               ret = msm_apm_switch_to_apcc(ctrl_dev);
 724 +               break;
 725 +       case MSM_APM_SUPPLY_MX:
 726 +               ret = msm_apm_switch_to_mx(ctrl_dev);
 727 +               break;
 728 +       default:
 729 +               ret = -EPERM;
 730 +               break;
 731 +       }
 732 +
 733 +       return ret;
 734 +}
 735 +EXPORT_SYMBOL(msm_apm_set_supply);
 736 +
 737 +/**
 738 + * msm_apm_ctrl_dev_get() - get a handle to the MSM APM controller linked to
 739 + *                          the device in device tree
 740 + * @dev:                    Pointer to the device
 741 + *
 742 + * The device must specify "qcom,apm-ctrl" property in its device tree
 743 + * node which points to an MSM APM controller device node.
 744 + *
 745 + * Returns an MSM APM controller handle if successful or ERR_PTR on any error.
 746 + * If the APM controller device hasn't probed yet, ERR_PTR(-EPROBE_DEFER) is
 747 + * returned.
 748 + */
 749 +struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
 750 +{
 751 +       struct msm_apm_ctrl_dev *ctrl_dev = NULL;
 752 +       struct msm_apm_ctrl_dev *dev_found = ERR_PTR(-EPROBE_DEFER);
 753 +       struct device_node *ctrl_node;
 754 +
 755 +       if (!dev || !dev->of_node) {
 756 +               pr_err("Invalid device node\n");
 757 +               return ERR_PTR(-EINVAL);
 758 +       }
 759 +
 760 +       ctrl_node = of_parse_phandle(dev->of_node, "qcom,apm-ctrl", 0);
 761 +       if (!ctrl_node) {
 762 +               pr_err("Could not find qcom,apm-ctrl property in %s\n",
 763 +                      dev->of_node->full_name);
 764 +               return ERR_PTR(-ENXIO);
 765 +       }
 766 +
 767 +       mutex_lock(&apm_ctrl_list_mutex);
 768 +       list_for_each_entry(ctrl_dev, &apm_ctrl_list, list) {
 769 +               if (ctrl_dev->dev && ctrl_dev->dev->of_node == ctrl_node) {
 770 +                       dev_found = ctrl_dev;
 771 +                       break;
 772 +               }
 773 +       }
 774 +       mutex_unlock(&apm_ctrl_list_mutex);
 775 +
 776 +       of_node_put(ctrl_node);
 777 +       return dev_found;
 778 +}
 779 +EXPORT_SYMBOL(msm_apm_ctrl_dev_get);
 780 +
 781 +#if defined(CONFIG_DEBUG_FS)
 782 +
 783 +static int apm_supply_dbg_open(struct inode *inode, struct file *filep)
 784 +{
 785 +       filep->private_data = inode->i_private;
 786 +
 787 +       return 0;
 788 +}
 789 +
 790 +static ssize_t apm_supply_dbg_read(struct file *filep, char __user *ubuf,
 791 +                                  size_t count, loff_t *ppos)
 792 +{
 793 +       struct msm_apm_ctrl_dev *ctrl_dev = filep->private_data;
 794 +       char buf[10];
 795 +       int len;
 796 +
 797 +       if (!ctrl_dev) {
 798 +               pr_err("invalid apm ctrl handle\n");
 799 +               return -ENODEV;
 800 +       }
 801 +
 802 +       if (ctrl_dev->supply == MSM_APM_SUPPLY_APCC)
 803 +               len = snprintf(buf, sizeof(buf), "APCC\n");
 804 +       else if (ctrl_dev->supply == MSM_APM_SUPPLY_MX)
 805 +               len = snprintf(buf, sizeof(buf), "MX\n");
 806 +       else
 807 +               len = snprintf(buf, sizeof(buf), "ERR\n");
 808 +
 809 +       return simple_read_from_buffer(ubuf, count, ppos, buf, len);
 810 +}
 811 +
 812 +static const struct file_operations apm_supply_fops = {
 813 +       .open = apm_supply_dbg_open,
 814 +       .read = apm_supply_dbg_read,
 815 +};
 816 +
 817 +static void apm_debugfs_base_init(void)
 818 +{
 819 +       apm_debugfs_base = debugfs_create_dir("msm-apm", NULL);
 820 +
 821 +       if (IS_ERR_OR_NULL(apm_debugfs_base))
 822 +               pr_err("msm-apm debugfs base directory creation failed\n");
 823 +}
 824 +
 825 +static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
 826 +{
 827 +       struct dentry *temp;
 828 +
 829 +       if (IS_ERR_OR_NULL(apm_debugfs_base)) {
 830 +               pr_err("Base directory missing, cannot create apm debugfs nodes\n");
 831 +               return;
 832 +       }
 833 +
 834 +       ctrl_dev->debugfs = debugfs_create_dir(dev_name(ctrl_dev->dev),
 835 +                                              apm_debugfs_base);
 836 +       if (IS_ERR_OR_NULL(ctrl_dev->debugfs)) {
 837 +               pr_err("%s debugfs directory creation failed\n",
 838 +                      dev_name(ctrl_dev->dev));
 839 +               return;
 840 +       }
 841 +
 842 +       temp = debugfs_create_file("supply", S_IRUGO, ctrl_dev->debugfs,
 843 +                                  ctrl_dev, &apm_supply_fops);
 844 +       if (IS_ERR_OR_NULL(temp)) {
 845 +               pr_err("supply mode creation failed\n");
 846 +               return;
 847 +       }
 848 +}
 849 +
 850 +static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
 851 +{
 852 +       if (!IS_ERR_OR_NULL(ctrl_dev->debugfs))
 853 +               debugfs_remove_recursive(ctrl_dev->debugfs);
 854 +}
 855 +
 856 +static void apm_debugfs_base_remove(void)
 857 +{
 858 +       debugfs_remove_recursive(apm_debugfs_base);
 859 +}
 860 +#else
 861 +
 862 +static void apm_debugfs_base_init(void)
 863 +{}
 864 +
 865 +static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
 866 +{}
 867 +
 868 +static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
 869 +{}
 870 +
 871 +static void apm_debugfs_base_remove(void)
 872 +{}
 873 +
 874 +#endif
 875 +
 876 +static struct of_device_id msm_apm_match_table[] = {
 877 +       {
 878 +               .compatible = "qcom,msm-apm",
 879 +               .data = (void *)(uintptr_t)MSM8996_ID,
 880 +       },
 881 +       {
 882 +               .compatible = "qcom,msm8953-apm",
 883 +               .data = (void *)(uintptr_t)MSM8953_ID,
 884 +       },
 885 +       {
 886 +               .compatible = "qcom,ipq807x-apm",
 887 +               .data = (void *)(uintptr_t)IPQ807x_ID,
 888 +       },
 889 +       {}
 890 +};
 891 +
 892 +static int msm_apm_probe(struct platform_device *pdev)
 893 +{
 894 +       struct device *dev = &pdev->dev;
 895 +       struct msm_apm_ctrl_dev *ctrl;
 896 +       const struct of_device_id *match;
 897 +       int ret = 0;
 898 +
 899 +       dev_dbg(dev, "probing MSM Array Power Mux driver\n");
 900 +
 901 +       if (!dev->of_node) {
 902 +               dev_err(dev, "Device tree node is missing\n");
 903 +               return -ENODEV;
 904 +       }
 905 +
 906 +       match = of_match_device(msm_apm_match_table, dev);
 907 +       if (!match)
 908 +               return -ENODEV;
 909 +
 910 +       ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
 911 +       if (!ctrl) {
 912 +               dev_err(dev, "MSM APM controller memory allocation failed\n");
 913 +               return -ENOMEM;
 914 +       }
 915 +
 916 +       INIT_LIST_HEAD(&ctrl->list);
 917 +       spin_lock_init(&ctrl->lock);
 918 +       ctrl->dev = dev;
 919 +       ctrl->msm_id = (uintptr_t)match->data;
 920 +       platform_set_drvdata(pdev, ctrl);
 921 +
 922 +       switch (ctrl->msm_id) {
 923 +       case MSM8996_ID:
 924 +               ret = msm_apm_ctrl_devm_ioremap(pdev, ctrl);
 925 +               if (ret) {
 926 +                       dev_err(dev, "Failed to add APM controller device\n");
 927 +                       return ret;
 928 +               }
 929 +               break;
 930 +       case MSM8953_ID:
 931 +       case IPQ807x_ID:
 932 +               ret = msm8953_apm_ctrl_init(pdev, ctrl);
 933 +               if (ret) {
 934 +                       dev_err(dev, "Failed to initialize APM controller device: ret=%d\n",
 935 +                               ret);
 936 +                       return ret;
 937 +               }
 938 +               break;
 939 +       default:
 940 +               dev_err(dev, "unable to add APM controller device for msm_id:%d\n",
 941 +                       ctrl->msm_id);
 942 +               return -ENODEV;
 943 +       }
 944 +
 945 +       apm_debugfs_init(ctrl);
 946 +       mutex_lock(&apm_ctrl_list_mutex);
 947 +       list_add_tail(&ctrl->list, &apm_ctrl_list);
 948 +       mutex_unlock(&apm_ctrl_list_mutex);
 949 +
 950 +       dev_dbg(dev, "MSM Array Power Mux driver probe successful");
 951 +
 952 +       return ret;
 953 +}
 954 +
 955 +static int msm_apm_remove(struct platform_device *pdev)
 956 +{
 957 +       struct msm_apm_ctrl_dev *ctrl_dev;
 958 +
 959 +       ctrl_dev = platform_get_drvdata(pdev);
 960 +       if (ctrl_dev) {
 961 +               mutex_lock(&apm_ctrl_list_mutex);
 962 +               list_del(&ctrl_dev->list);
 963 +               mutex_unlock(&apm_ctrl_list_mutex);
 964 +               apm_debugfs_deinit(ctrl_dev);
 965 +       }
 966 +
 967 +       return 0;
 968 +}
 969 +
 970 +static struct platform_driver msm_apm_driver = {
 971 +       .driver         = {
 972 +               .name           = MSM_APM_DRIVER_NAME,
 973 +               .of_match_table = msm_apm_match_table,
 974 +               .owner          = THIS_MODULE,
 975 +       },
 976 +       .probe          = msm_apm_probe,
 977 +       .remove         = msm_apm_remove,
 978 +};
 979 +
 980 +static int __init msm_apm_init(void)
 981 +{
 982 +       apm_debugfs_base_init();
 983 +       return platform_driver_register(&msm_apm_driver);
 984 +}
 985 +
 986 +static void __exit msm_apm_exit(void)
 987 +{
 988 +       platform_driver_unregister(&msm_apm_driver);
 989 +       apm_debugfs_base_remove();
 990 +}
 991 +
 992 +arch_initcall(msm_apm_init);
 993 +module_exit(msm_apm_exit);
 994 +
 995 +MODULE_DESCRIPTION("MSM Array Power Mux driver");
 996 +MODULE_LICENSE("GPL v2");
 997 --- /dev/null
 998 +++ b/include/linux/power/qcom/apm.h
 999 @@ -0,0 +1,48 @@
1000 +/*
1001 + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
1002 + *
1003 + * This program is free software; you can redistribute it and/or modify
1004 + * it under the terms of the GNU General Public License version 2 and
1005 + * only version 2 as published by the Free Software Foundation.
1006 + *
1007 + * This program is distributed in the hope that it will be useful,
1008 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1009 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1010 + * GNU General Public License for more details.
1011 + */
1012 +
1013 +#ifndef __LINUX_POWER_QCOM_APM_H__
1014 +#define __LINUX_POWER_QCOM_APM_H__
1015 +
1016 +#include <linux/device.h>
1017 +#include <linux/err.h>
1018 +
1019 +/**
1020 + * enum msm_apm_supply - supported power rails to supply memory arrays
1021 + * %MSM_APM_SUPPLY_APCC:       to enable selection of VDD_APCC rail as supply
1022 + * %MSM_APM_SUPPLY_MX:         to enable selection of VDD_MX rail as supply
1023 + */
1024 +enum msm_apm_supply {
1025 +       MSM_APM_SUPPLY_APCC,
1026 +       MSM_APM_SUPPLY_MX,
1027 +};
1028 +
1029 +/* Handle used to identify an APM controller device  */
1030 +struct msm_apm_ctrl_dev;
1031 +
1032 +#ifdef CONFIG_QCOM_APM
1033 +struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev);
1034 +int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
1035 +                      enum msm_apm_supply supply);
1036 +int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev);
1037 +
1038 +#else
1039 +static inline struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
1040 +{ return ERR_PTR(-EPERM); }
1041 +static inline int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
1042 +                      enum msm_apm_supply supply)
1043 +{ return -EPERM; }
1044 +static inline int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
1045 +{ return -EPERM; }
1046 +#endif
1047 +#endif