mediatek: mt7629: 6.6: disable LEDS_SMARTRG_LED by default
[openwrt/staging/stintel.git] / target / linux / qualcommax / patches-6.1 / 0026-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch
1 From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Fri, 13 Oct 2023 19:20:02 +0200
4 Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
5
6 IPQ8074 comes in 3 families:
7 * IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
8 * IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
9 * IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
10
11 So, in order to be able to share one OPP table lets add support for IPQ8074
12 family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
13
14 IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
15 will get created by NVMEM CPUFreq driver.
16
17 Signed-off-by: Robert Marko <robimarko@gmail.com>
18 Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
19 [ Viresh: Fixed rebase conflict. ]
20 Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
21 ---
22 drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
23 drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
24 2 files changed, 49 insertions(+)
25
26 --- a/drivers/cpufreq/cpufreq-dt-platdev.c
27 +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
28 @@ -165,6 +165,7 @@ static const struct of_device_id blockli
29
30 { .compatible = "qcom,ipq6018", },
31 { .compatible = "qcom,ipq8064", },
32 + { .compatible = "qcom,ipq8074", },
33 { .compatible = "qcom,apq8064", },
34 { .compatible = "qcom,msm8974", },
35 { .compatible = "qcom,msm8960", },
36 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
37 +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
38 @@ -33,6 +33,11 @@
39
40 #define IPQ6000_VERSION BIT(2)
41
42 +enum ipq8074_versions {
43 + IPQ8074_HAWKEYE_VERSION = 0,
44 + IPQ8074_ACORN_VERSION,
45 +};
46 +
47 struct qcom_cpufreq_drv;
48
49 struct qcom_cpufreq_match_data {
50 @@ -257,6 +262,44 @@ static int qcom_cpufreq_ipq6018_name_ver
51 return 0;
52 }
53
54 +static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
55 + struct nvmem_cell *speedbin_nvmem,
56 + char **pvs_name,
57 + struct qcom_cpufreq_drv *drv)
58 +{
59 + u32 msm_id;
60 + int ret;
61 + *pvs_name = NULL;
62 +
63 + ret = qcom_smem_get_soc_id(&msm_id);
64 + if (ret)
65 + return ret;
66 +
67 + switch (msm_id) {
68 + case QCOM_ID_IPQ8070A:
69 + case QCOM_ID_IPQ8071A:
70 + case QCOM_ID_IPQ8172:
71 + case QCOM_ID_IPQ8173:
72 + case QCOM_ID_IPQ8174:
73 + drv->versions = BIT(IPQ8074_ACORN_VERSION);
74 + break;
75 + case QCOM_ID_IPQ8072A:
76 + case QCOM_ID_IPQ8074A:
77 + case QCOM_ID_IPQ8076A:
78 + case QCOM_ID_IPQ8078A:
79 + drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
80 + break;
81 + default:
82 + dev_err(cpu_dev,
83 + "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
84 + msm_id);
85 + drv->versions = BIT(IPQ8074_ACORN_VERSION);
86 + break;
87 + }
88 +
89 + return 0;
90 +}
91 +
92 static const struct qcom_cpufreq_match_data match_data_kryo = {
93 .get_version = qcom_cpufreq_kryo_name_version,
94 };
95 @@ -275,6 +318,10 @@ static const struct qcom_cpufreq_match_d
96 .get_version = qcom_cpufreq_ipq6018_name_version,
97 };
98
99 +static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
100 + .get_version = qcom_cpufreq_ipq8074_name_version,
101 +};
102 +
103 static int qcom_cpufreq_probe(struct platform_device *pdev)
104 {
105 struct qcom_cpufreq_drv *drv;
106 @@ -421,6 +468,7 @@ static const struct of_device_id qcom_cp
107 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
108 { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
109 { .compatible = "qcom,ipq8064", .data = &match_data_krait },
110 + { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
111 { .compatible = "qcom,apq8064", .data = &match_data_krait },
112 { .compatible = "qcom,msm8974", .data = &match_data_krait },
113 { .compatible = "qcom,msm8960", .data = &match_data_krait },