target/linux/qualcommax/patches-6.1/0026-v6.7-clk-qcom-ipq8074-drop-the-CLK_SET_RATE_PARENT-flag-f.patch

   1 From 007ad475ba7f0d5d4d3e43a06e46a8a46d31c9d2 Mon Sep 17 00:00:00 2001
   2 From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
   3 Date: Thu, 14 Sep 2023 12:29:51 +0530
   4 Subject: [PATCH] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from
   5  PLL clocks
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based
  11 on the request from dependent clocks. Doing so will result in the
  12 unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL
  13 clocks.
  14
  15 Cc: stable@vger.kernel.org
  16 Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
  17 Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
  18 ---
  19  drivers/clk/qcom/gcc-ipq8074.c | 6 ------
  20  1 file changed, 6 deletions(-)
  21
  22 --- a/drivers/clk/qcom/gcc-ipq8074.c
  23 +++ b/drivers/clk/qcom/gcc-ipq8074.c
  24 @@ -76,7 +76,6 @@ static struct clk_fixed_factor gpll0_out
  25                                 &gpll0_main.clkr.hw },
  26                 .num_parents = 1,
  27                 .ops = &clk_fixed_factor_ops,
  28 -               .flags = CLK_SET_RATE_PARENT,
  29         },
  30  };
  31
  32 @@ -122,7 +121,6 @@ static struct clk_alpha_pll_postdiv gpll
  33                                 &gpll2_main.clkr.hw },
  34                 .num_parents = 1,
  35                 .ops = &clk_alpha_pll_postdiv_ro_ops,
  36 -               .flags = CLK_SET_RATE_PARENT,
  37         },
  38  };
  39
  40 @@ -155,7 +153,6 @@ static struct clk_alpha_pll_postdiv gpll
  41                                 &gpll4_main.clkr.hw },
  42                 .num_parents = 1,
  43                 .ops = &clk_alpha_pll_postdiv_ro_ops,
  44 -               .flags = CLK_SET_RATE_PARENT,
  45         },
  46  };
  47
  48 @@ -189,7 +186,6 @@ static struct clk_alpha_pll_postdiv gpll
  49                                 &gpll6_main.clkr.hw },
  50                 .num_parents = 1,
  51                 .ops = &clk_alpha_pll_postdiv_ro_ops,
  52 -               .flags = CLK_SET_RATE_PARENT,
  53         },
  54  };
  55
  56 @@ -202,7 +198,6 @@ static struct clk_fixed_factor gpll6_out
  57                                 &gpll6_main.clkr.hw },
  58                 .num_parents = 1,
  59                 .ops = &clk_fixed_factor_ops,
  60 -               .flags = CLK_SET_RATE_PARENT,
  61         },
  62  };
  63
  64 @@ -267,7 +262,6 @@ static struct clk_alpha_pll_postdiv nss_
  65                                 &nss_crypto_pll_main.clkr.hw },
  66                 .num_parents = 1,
  67                 .ops = &clk_alpha_pll_postdiv_ro_ops,
  68 -               .flags = CLK_SET_RATE_PARENT,
  69         },
  70  };
  71