target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include <dt-bindings/net/qcom-ipq-ess.h>
   4
   5 &clocks {
   6         bias_pll_cc_clk {
   7                 compatible = "fixed-clock";
   8                 clock-frequency = <300000000>;
   9                 #clock-cells = <0>;
  10         };
  11
  12         bias_pll_nss_noc_clk {
  13                 compatible = "fixed-clock";
  14                 clock-frequency = <416500000>;
  15                 #clock-cells = <0>;
  16         };
  17 };
  18
  19 &soc {
  20         switch: ess-switch@3a000000 {
  21                 compatible = "qcom,ess-switch-ipq807x";
  22                 reg = <0x3a000000 0x1000000>;
  23                 switch_access_mode = "local bus";
  24                 switch_cpu_bmp = <ESS_PORT0>;  /* cpu port bitmap */
  25                 switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
  26                 /* This is a special binding that controls how the malibu PHY are
  27                  * init. This value reflect the PHY addr of the first malibu PHY.
  28                  * Malibu PHY are in a bundle of 5 PHY.
  29                  * Some device might have some port not connected.
  30                  * SSDK still needs the addrs of the first PHY (even if not connected)
  31                  * to correctly setup the malibu PHY.
  32                  *
  33                  * This is needed as previously SSDK based this on the port bmp, but
  34                  * this can be problematic now that we specify correct bmp.
  35                  *
  36                  * Most common configuration have the malibu PHY placed at 0.
  37                  * But some device might have it placed at address 16.
  38                  * To drive the correct value, check the port id of the malibu PHY
  39                  * and try to understand what is the first one in devices where some
  40                  * port are missing. port_phyinfo is normally the way to go to derive
  41                  * this value in the few special cases.
  42                  */
  43                 malibu_first_phy_addr = <0>;
  44                 clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
  45                          <&gcc GCC_CMN_12GPLL_SYS_CLK>,
  46                          <&gcc GCC_UNIPHY0_AHB_CLK>,
  47                          <&gcc GCC_UNIPHY0_SYS_CLK>,
  48                          <&gcc GCC_UNIPHY1_AHB_CLK>,
  49                          <&gcc GCC_UNIPHY1_SYS_CLK>,
  50                          <&gcc GCC_UNIPHY2_AHB_CLK>,
  51                          <&gcc GCC_UNIPHY2_SYS_CLK>,
  52                          <&gcc GCC_PORT1_MAC_CLK>,
  53                          <&gcc GCC_PORT2_MAC_CLK>,
  54                          <&gcc GCC_PORT3_MAC_CLK>,
  55                          <&gcc GCC_PORT4_MAC_CLK>,
  56                          <&gcc GCC_PORT5_MAC_CLK>,
  57                          <&gcc GCC_PORT6_MAC_CLK>,
  58                          <&gcc GCC_NSS_PPE_CLK>,
  59                          <&gcc GCC_NSS_PPE_CFG_CLK>,
  60                          <&gcc GCC_NSSNOC_PPE_CLK>,
  61                          <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
  62                          <&gcc GCC_NSS_EDMA_CLK>,
  63                          <&gcc GCC_NSS_EDMA_CFG_CLK>,
  64                          <&gcc GCC_NSS_PPE_IPE_CLK>,
  65                          <&gcc GCC_NSS_PPE_BTQ_CLK>,
  66                          <&gcc GCC_MDIO_AHB_CLK>,
  67                          <&gcc GCC_NSS_NOC_CLK>,
  68                          <&gcc GCC_NSSNOC_SNOC_CLK>,
  69                          <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
  70                          <&gcc GCC_NSS_CRYPTO_CLK>,
  71                          <&gcc GCC_NSS_IMEM_CLK>,
  72                          <&gcc GCC_NSS_PTP_REF_CLK>,
  73                          <&gcc GCC_NSS_PORT1_RX_CLK>,
  74                          <&gcc GCC_NSS_PORT1_TX_CLK>,
  75                          <&gcc GCC_NSS_PORT2_RX_CLK>,
  76                          <&gcc GCC_NSS_PORT2_TX_CLK>,
  77                          <&gcc GCC_NSS_PORT3_RX_CLK>,
  78                          <&gcc GCC_NSS_PORT3_TX_CLK>,
  79                          <&gcc GCC_NSS_PORT4_RX_CLK>,
  80                          <&gcc GCC_NSS_PORT4_TX_CLK>,
  81                          <&gcc GCC_NSS_PORT5_RX_CLK>,
  82                          <&gcc GCC_NSS_PORT5_TX_CLK>,
  83                          <&gcc GCC_NSS_PORT6_RX_CLK>,
  84                          <&gcc GCC_NSS_PORT6_TX_CLK>,
  85                          <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
  86                          <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
  87                          <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
  88                          <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
  89                          <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
  90                          <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
  91                          <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
  92                          <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
  93                          <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
  94                          <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
  95                          <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
  96                          <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
  97                          <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
  98                          <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
  99                          <&gcc NSS_PORT5_RX_CLK_SRC>,
 100                          <&gcc NSS_PORT5_TX_CLK_SRC>;
 101                 clock-names = "cmn_ahb_clk", "cmn_sys_clk",
 102                               "uniphy0_ahb_clk", "uniphy0_sys_clk",
 103                               "uniphy1_ahb_clk", "uniphy1_sys_clk",
 104                               "uniphy2_ahb_clk", "uniphy2_sys_clk",
 105                               "port1_mac_clk", "port2_mac_clk",
 106                               "port3_mac_clk", "port4_mac_clk",
 107                               "port5_mac_clk", "port6_mac_clk",
 108                               "nss_ppe_clk", "nss_ppe_cfg_clk",
 109                               "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
 110                               "nss_edma_clk", "nss_edma_cfg_clk",
 111                               "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
 112                               "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
 113                               "gcc_nssnoc_snoc_clk",
 114                               "gcc_mem_noc_nss_axi_clk",
 115                               "gcc_nss_crypto_clk",
 116                               "gcc_nss_imem_clk",
 117                               "gcc_nss_ptp_ref_clk",
 118                               "nss_port1_rx_clk", "nss_port1_tx_clk",
 119                               "nss_port2_rx_clk", "nss_port2_tx_clk",
 120                               "nss_port3_rx_clk", "nss_port3_tx_clk",
 121                               "nss_port4_rx_clk", "nss_port4_tx_clk",
 122                               "nss_port5_rx_clk", "nss_port5_tx_clk",
 123                               "nss_port6_rx_clk", "nss_port6_tx_clk",
 124                               "uniphy0_port1_rx_clk",
 125                               "uniphy0_port1_tx_clk",
 126                               "uniphy0_port2_rx_clk",
 127                               "uniphy0_port2_tx_clk",
 128                               "uniphy0_port3_rx_clk",
 129                               "uniphy0_port3_tx_clk",
 130                               "uniphy0_port4_rx_clk",
 131                               "uniphy0_port4_tx_clk",
 132                               "uniphy0_port5_rx_clk",
 133                               "uniphy0_port5_tx_clk",
 134                               "uniphy1_port5_rx_clk",
 135                               "uniphy1_port5_tx_clk",
 136                               "uniphy2_port6_rx_clk",
 137                               "uniphy2_port6_tx_clk",
 138                               "nss_port5_rx_clk_src",
 139                               "nss_port5_tx_clk_src";
 140                 resets = <&gcc GCC_PPE_FULL_RESET>,
 141                          <&gcc GCC_UNIPHY0_SOFT_RESET>,
 142                          <&gcc GCC_UNIPHY0_XPCS_RESET>,
 143                          <&gcc GCC_UNIPHY1_SOFT_RESET>,
 144                          <&gcc GCC_UNIPHY1_XPCS_RESET>,
 145                          <&gcc GCC_UNIPHY2_SOFT_RESET>,
 146                          <&gcc GCC_UNIPHY2_XPCS_RESET>,
 147                          <&gcc GCC_NSSPORT1_RESET>,
 148                          <&gcc GCC_NSSPORT2_RESET>,
 149                          <&gcc GCC_NSSPORT3_RESET>,
 150                          <&gcc GCC_NSSPORT4_RESET>,
 151                          <&gcc GCC_NSSPORT5_RESET>,
 152                          <&gcc GCC_NSSPORT6_RESET>;
 153                 reset-names = "ppe_rst", "uniphy0_soft_rst",
 154                               "uniphy0_xpcs_rst", "uniphy1_soft_rst",
 155                               "uniphy1_xpcs_rst", "uniphy2_soft_rst",
 156                               "uniphy2_xpcs_rst", "nss_port1_rst",
 157                               "nss_port2_rst", "nss_port3_rst",
 158                               "nss_port4_rst", "nss_port5_rst",
 159                               "nss_port6_rst";
 160                 mdio-bus = <&mdio>;
 161
 162                 switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
 163                 switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
 164                 switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
 165
 166                 bm_tick_mode = <0>; /* bm tick mode */
 167                 tm_tick_mode = <0>; /* tm tick mode */
 168
 169                 status = "disabled";
 170
 171                 port_scheduler_resource {
 172                         port@0 {
 173                                 port_id = <0>;
 174                                 ucast_queue = <0 143>;
 175                                 mcast_queue = <256 271>;
 176                                 l0sp = <0 35>;
 177                                 l0cdrr = <0 47>;
 178                                 l0edrr = <0 47>;
 179                                 l1cdrr = <0 7>;
 180                                 l1edrr = <0 7>;
 181                         };
 182                         port@1 {
 183                                 port_id = <1>;
 184                                 ucast_queue = <144 159>;
 185                                 mcast_queue = <272 275>;
 186                                 l0sp = <36 39>;
 187                                 l0cdrr = <48 63>;
 188                                 l0edrr = <48 63>;
 189                                 l1cdrr = <8 11>;
 190                                 l1edrr = <8 11>;
 191                         };
 192                         port@2 {
 193                                 port_id = <2>;
 194                                 ucast_queue = <160 175>;
 195                                 mcast_queue = <276 279>;
 196                                 l0sp = <40 43>;
 197                                 l0cdrr = <64 79>;
 198                                 l0edrr = <64 79>;
 199                                 l1cdrr = <12 15>;
 200                                 l1edrr = <12 15>;
 201                         };
 202                         port@3 {
 203                                 port_id = <3>;
 204                                 ucast_queue = <176 191>;
 205                                 mcast_queue = <280 283>;
 206                                 l0sp = <44 47>;
 207                                 l0cdrr = <80 95>;
 208                                 l0edrr = <80 95>;
 209                                 l1cdrr = <16 19>;
 210                                 l1edrr = <16 19>;
 211                         };
 212                         port@4 {
 213                                 port_id = <4>;
 214                                 ucast_queue = <192 207>;
 215                                 mcast_queue = <284 287>;
 216                                 l0sp = <48 51>;
 217                                 l0cdrr = <96 111>;
 218                                 l0edrr = <96 111>;
 219                                 l1cdrr = <20 23>;
 220                                 l1edrr = <20 23>;
 221                         };
 222                         port@5 {
 223                                 port_id = <5>;
 224                                 ucast_queue = <208 223>;
 225                                 mcast_queue = <288 291>;
 226                                 l0sp = <52 55>;
 227                                 l0cdrr = <112 127>;
 228                                 l0edrr = <112 127>;
 229                                 l1cdrr = <24 27>;
 230                                 l1edrr = <24 27>;
 231                         };
 232                         port@6 {
 233                                 port_id = <6>;
 234                                 ucast_queue = <224 239>;
 235                                 mcast_queue = <292 295>;
 236                                 l0sp = <56 59>;
 237                                 l0cdrr = <128 143>;
 238                                 l0edrr = <128 143>;
 239                                 l1cdrr = <28 31>;
 240                                 l1edrr = <28 31>;
 241                         };
 242                         port@7 {
 243                                 port_id = <7>;
 244                                 ucast_queue = <240 255>;
 245                                 mcast_queue = <296 299>;
 246                                 l0sp = <60 63>;
 247                                 l0cdrr = <144 159>;
 248                                 l0edrr = <144 159>;
 249                                 l1cdrr = <32 35>;
 250                                 l1edrr = <32 35>;
 251                         };
 252                 };
 253                 port_scheduler_config {
 254                         port@0 {
 255                                 port_id = <0>;
 256                                 l1scheduler {
 257                                         group@0 {
 258                                                 sp = <0 1>; /*L0 SPs*/
 259                                                 /*cpri cdrr epri edrr*/
 260                                                 cfg = <0 0 0 0>;
 261                                         };
 262                                 };
 263                                 l0scheduler {
 264                                         group@0 {
 265                                                 /*unicast queues*/
 266                                                 ucast_queue = <0 4 8>;
 267                                                 /*multicast queues*/
 268                                                 mcast_queue = <256 260>;
 269                                                 /*sp cpri cdrr epri edrr*/
 270                                                 cfg = <0 0 0 0 0>;
 271                                         };
 272                                         group@1 {
 273                                                 ucast_queue = <1 5 9>;
 274                                                 mcast_queue = <257 261>;
 275                                                 cfg = <0 1 1 1 1>;
 276                                         };
 277                                         group@2 {
 278                                                 ucast_queue = <2 6 10>;
 279                                                 mcast_queue = <258 262>;
 280                                                 cfg = <0 2 2 2 2>;
 281                                         };
 282                                         group@3 {
 283                                                 ucast_queue = <3 7 11>;
 284                                                 mcast_queue = <259 263>;
 285                                                 cfg = <0 3 3 3 3>;
 286                                         };
 287                                 };
 288                         };
 289                         port@1 {
 290                                 port_id = <1>;
 291                                 l1scheduler {
 292                                         group@0 {
 293                                                 sp = <36>;
 294                                                 cfg = <0 8 0 8>;
 295                                         };
 296                                         group@1 {
 297                                                 sp = <37>;
 298                                                 cfg = <1 9 1 9>;
 299                                         };
 300                                 };
 301                                 l0scheduler {
 302                                         group@0 {
 303                                                 ucast_queue = <144>;
 304                                                 ucast_loop_pri = <16>;
 305                                                 mcast_queue = <272>;
 306                                                 mcast_loop_pri = <4>;
 307                                                 cfg = <36 0 48 0 48>;
 308                                         };
 309                                 };
 310                         };
 311                         port@2 {
 312                                 port_id = <2>;
 313                                 l1scheduler {
 314                                         group@0 {
 315                                                 sp = <40>;
 316                                                 cfg = <0 12 0 12>;
 317                                         };
 318                                         group@1 {
 319                                                 sp = <41>;
 320                                                 cfg = <1 13 1 13>;
 321                                         };
 322                                 };
 323                                 l0scheduler {
 324                                         group@0 {
 325                                                 ucast_queue = <160>;
 326                                                 ucast_loop_pri = <16>;
 327                                                 mcast_queue = <276>;
 328                                                 mcast_loop_pri = <4>;
 329                                                 cfg = <40 0 64 0 64>;
 330                                         };
 331                                 };
 332                         };
 333                         port@3 {
 334                                 port_id = <3>;
 335                                 l1scheduler {
 336                                         group@0 {
 337                                                 sp = <44>;
 338                                                 cfg = <0 16 0 16>;
 339                                         };
 340                                         group@1 {
 341                                                 sp = <45>;
 342                                                 cfg = <1 17 1 17>;
 343                                         };
 344                                 };
 345                                 l0scheduler {
 346                                         group@0 {
 347                                                 ucast_queue = <176>;
 348                                                 ucast_loop_pri = <16>;
 349                                                 mcast_queue = <280>;
 350                                                 mcast_loop_pri = <4>;
 351                                                 cfg = <44 0 80 0 80>;
 352                                         };
 353                                 };
 354                         };
 355                         port@4 {
 356                                 port_id = <4>;
 357                                 l1scheduler {
 358                                         group@0 {
 359                                                 sp = <48>;
 360                                                 cfg = <0 20 0 20>;
 361                                         };
 362                                         group@1 {
 363                                                 sp = <49>;
 364                                                 cfg = <1 21 1 21>;
 365                                         };
 366                                 };
 367                                 l0scheduler {
 368                                         group@0 {
 369                                                 ucast_queue = <192>;
 370                                                 ucast_loop_pri = <16>;
 371                                                 mcast_queue = <284>;
 372                                                 mcast_loop_pri = <4>;
 373                                                 cfg = <48 0 96 0 96>;
 374                                         };
 375                                 };
 376                         };
 377                         port@5 {
 378                                 port_id = <5>;
 379                                 l1scheduler {
 380                                         group@0 {
 381                                                 sp = <52>;
 382                                                 cfg = <0 24 0 24>;
 383                                         };
 384                                         group@1 {
 385                                                 sp = <53>;
 386                                                 cfg = <1 25 1 25>;
 387                                         };
 388                                 };
 389                                 l0scheduler {
 390                                         group@0 {
 391                                                 ucast_queue = <208>;
 392                                                 ucast_loop_pri = <16>;
 393                                                 mcast_queue = <288>;
 394                                                 mcast_loop_pri = <4>;
 395                                                 cfg = <52 0 112 0 112>;
 396                                         };
 397                                 };
 398                         };
 399                         port@6 {
 400                                 port_id = <6>;
 401                                 l1scheduler {
 402                                         group@0 {
 403                                                 sp = <56>;
 404                                                 cfg = <0 28 0 28>;
 405                                         };
 406                                         group@1 {
 407                                                 sp = <57>;
 408                                                 cfg = <1 29 1 29>;
 409                                         };
 410                                 };
 411                                 l0scheduler {
 412                                         group@0 {
 413                                                 ucast_queue = <224>;
 414                                                 ucast_loop_pri = <16>;
 415                                                 mcast_queue = <292>;
 416                                                 mcast_loop_pri = <4>;
 417                                                 cfg = <56 0 128 0 128>;
 418                                         };
 419                                 };
 420                         };
 421                         port@7 {
 422                                 port_id = <7>;
 423                                 l1scheduler {
 424                                         group@0 {
 425                                                 sp = <60>;
 426                                                 cfg = <0 32 0 32>;
 427                                         };
 428                                         group@1 {
 429                                                 sp = <61>;
 430                                                 cfg = <1 33 1 33>;
 431                                         };
 432                                 };
 433                                 l0scheduler {
 434                                         group@0 {
 435                                                 ucast_queue = <240>;
 436                                                 ucast_loop_pri = <16>;
 437                                                 mcast_queue = <296>;
 438                                                 cfg = <60 0 144 0 144>;
 439                                         };
 440                                 };
 441                         };
 442                 };
 443         };
 444
 445         ess-uniphy@7a00000 {
 446                 compatible = "qcom,ess-uniphy";
 447                 reg = <0x7a00000 0x30000>;
 448                 uniphy_access_mode = "local bus";
 449         };
 450
 451         edma: edma@3ab00000 {
 452                 compatible = "qcom,edma";
 453                 reg = <0x3ab00000 0x76900>;
 454                 reg-names = "edma-reg-base";
 455                 qcom,txdesc-ring-start = <23>;
 456                 qcom,txdesc-rings = <1>;
 457                 qcom,txcmpl-ring-start = <7>;
 458                 qcom,txcmpl-rings = <1>;
 459                 qcom,rxfill-ring-start = <7>;
 460                 qcom,rxfill-rings = <1>;
 461                 qcom,rxdesc-ring-start = <15>;
 462                 qcom,rxdesc-rings = <1>;
 463                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 464                              <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 465                              <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 466                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 467                 resets = <&gcc GCC_EDMA_HW_RESET>;
 468                 reset-names = "edma_rst";
 469                 status = "disabled";
 470         };
 471
 472         dp1: dp1@3a001000 {
 473                 device_type = "network";
 474                 compatible = "qcom,nss-dp";
 475                 qcom,id = <1>;
 476                 reg = <0x3a001000 0x200>;
 477                 qcom,mactype = <0>;
 478                 local-mac-address = [000000000000];
 479                 phy-mode = "sgmii";
 480                 status = "disabled";
 481         };
 482
 483         dp2: dp2@3a001200 {
 484                 device_type = "network";
 485                 compatible = "qcom,nss-dp";
 486                 qcom,id = <2>;
 487                 reg = <0x3a001200 0x200>;
 488                 qcom,mactype = <0>;
 489                 local-mac-address = [000000000000];
 490                 phy-mode = "sgmii";
 491                 status = "disabled";
 492         };
 493
 494         dp3: dp3@3a001400 {
 495                 device_type = "network";
 496                 compatible = "qcom,nss-dp";
 497                 qcom,id = <3>;
 498                 reg = <0x3a001400 0x200>;
 499                 qcom,mactype = <0>;
 500                 local-mac-address = [000000000000];
 501                 phy-mode = "sgmii";
 502                 status = "disabled";
 503         };
 504
 505         dp4: dp4@3a001600 {
 506                 device_type = "network";
 507                 compatible = "qcom,nss-dp";
 508                 qcom,id = <4>;
 509                 reg = <0x3a001600 0x200>;
 510                 qcom,mactype = <0>;
 511                 local-mac-address = [000000000000];
 512                 phy-mode = "sgmii";
 513                 status = "disabled";
 514         };
 515
 516         dp5: dp5@3a001800 {
 517                 device_type = "network";
 518                 compatible = "qcom,nss-dp";
 519                 qcom,id = <5>;
 520                 reg = <0x3a001800 0x200>;
 521                 qcom,mactype = <0>;
 522                 local-mac-address = [000000000000];
 523                 phy-mode = "sgmii";
 524                 status = "disabled";
 525         };
 526
 527         dp6: dp6@3a001a00 {
 528                 device_type = "network";
 529                 compatible = "qcom,nss-dp";
 530                 qcom,id = <6>;
 531                 reg = <0x3a001a00 0x200>;
 532                 qcom,mactype = <0>;
 533                 local-mac-address = [000000000000];
 534                 phy-mode = "sgmii";
 535                 status = "disabled";
 536         };
 537
 538         dp5_syn: dp5-syn@3a003000 {
 539                 device_type = "network";
 540                 compatible = "qcom,nss-dp";
 541                 qcom,id = <5>;
 542                 reg = <0x3a003000 0x3fff>;
 543                 qcom,mactype = <1>;
 544                 local-mac-address = [000000000000];
 545                 phy-mode = "sgmii";
 546                 status = "disabled";
 547         };
 548
 549         dp6_syn: dp6-syn@3a007000 {
 550                 device_type = "network";
 551                 compatible = "qcom,nss-dp";
 552                 qcom,id = <6>;
 553                 reg = <0x3a007000 0x3fff>;
 554                 qcom,mactype = <1>;
 555                 local-mac-address = [000000000000];
 556                 phy-mode = "sgmii";
 557                 status = "disabled";
 558         };
 559 };