ipq807x: add support for Zbtlink ZBT-Z800AX
[openwrt/staging/stintel.git] / target / linux / qualcommax / files / arch / arm64 / boot / dts / qcom / ipq8072-zbt-z800ax.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 /dts-v1/;
4
5 #include "ipq8074.dtsi"
6 #include "ipq8074-hk-cpu.dtsi"
7 #include "ipq8074-ess.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11
12 / {
13 model = "Zbtlink ZBT-Z800AX";
14 compatible = "zbtlink,zbt-z800ax", "qcom,ipq8074";
15
16 aliases {
17 led-boot = &led_net;
18 led-failsafe = &led_net;
19 led-upgrade = &led_net;
20 serial0 = &blsp1_uart5;
21 /*
22 * Aliases as required by u-boot
23 * to patch MAC addresses
24 */
25 ethernet0 = &dp1;
26 ethernet1 = &dp2;
27 ethernet2 = &dp3;
28 ethernet3 = &dp4;
29 ethernet4 = &dp5;
30 label-mac-device = &dp1;
31 };
32
33 chosen {
34 stdout-path = "serial0:115200n8";
35 bootargs-append = " root=/dev/ubiblock0_1";
36 };
37
38 gpio-export {
39 compatible = "gpio-export";
40
41 lte-power {
42 gpio-export,name = "lte_power";
43 gpio-export,output = <1>;
44 gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
45 };
46 };
47
48 keys {
49 compatible = "gpio-keys";
50 pinctrl-0 = <&button_pins>;
51 pinctrl-names = "default";
52
53 reset {
54 label = "reset";
55 linux,code = <KEY_RESTART>;
56 gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
57 };
58
59 wps {
60 label = "wps";
61 linux,code = <KEY_WPS_BUTTON>;
62 gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
63 };
64 };
65
66 leds {
67 compatible = "gpio-leds";
68
69 led_net: net {
70 color = <LED_COLOR_ID_GREEN>;
71 function = LED_FUNCTION_WAN_ONLINE;
72 gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
73 };
74
75 module {
76 color = <LED_COLOR_ID_GREEN>;
77 function = LED_FUNCTION_MOBILE;
78 gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
79 };
80
81 wlan2g {
82 color = <LED_COLOR_ID_GREEN>;
83 function = LED_FUNCTION_WLAN_2GHZ;
84 gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
85 linux,default-trigger = "phy1radio";
86 };
87
88 wlan5g {
89 color = <LED_COLOR_ID_GREEN>;
90 function = LED_FUNCTION_WLAN_5GHZ;
91 gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
92 linux,default-trigger = "phy0radio";
93 };
94 };
95 };
96
97 &tlmm {
98 button_pins: button-pins {
99 mux {
100 pins = "gpio34", "gpio46";
101 function = "gpio";
102 drive-strength = <8>;
103 bias-pull-up;
104 };
105 };
106
107 mdio_pins: mdio-pins {
108 mdc {
109 pins = "gpio68";
110 function = "mdc";
111 drive-strength = <8>;
112 bias-pull-up;
113 };
114
115 mdio {
116 pins = "gpio69";
117 function = "mdio";
118 drive-strength = <8>;
119 bias-pull-up;
120 };
121 };
122 };
123
124 &blsp1_spi1 {
125 pinctrl-0 = <&spi_0_pins>;
126 pinctrl-names = "default";
127 cs-select = <0>;
128 status = "okay";
129
130 flash@0 {
131 compatible = "jedec,spi-nor";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 reg = <0>;
135 spi-max-frequency = <50000000>;
136
137 partitions {
138 compatible = "fixed-partitions";
139 #address-cells = <1>;
140 #size-cells = <1>;
141
142 partition@0 {
143 label = "0:sbl1";
144 reg = <0x0 0x50000>;
145 read-only;
146 };
147
148 partition@50000 {
149 label = "0:mibib";
150 reg = <0x50000 0x10000>;
151 read-only;
152 };
153
154 partition@60000 {
155 label = "0:bootconfig";
156 reg = <0x60000 0x20000>;
157 read-only;
158 };
159
160 partition@80000 {
161 label = "0:bootconfig1";
162 reg = <0x80000 0x20000>;
163 read-only;
164 };
165
166 partition@a0000 {
167 label = "0:qsee";
168 reg = <0xa0000 0x180000>;
169 read-only;
170 };
171
172 partition@220000 {
173 label = "0:qsee_1";
174 reg = <0x220000 0x180000>;
175 read-only;
176 };
177
178 partition@3a0000 {
179 label = "0:devcfg";
180 reg = <0x3a0000 0x10000>;
181 read-only;
182 };
183
184 partition@3b0000 {
185 label = "0:devcfg_1";
186 reg = <0x3b0000 0x10000>;
187 read-only;
188 };
189
190 partition@3c0000 {
191 label = "0:apdp";
192 reg = <0x3c0000 0x10000>;
193 read-only;
194 };
195
196 partition@3d0000 {
197 label = "0:apdp_1";
198 reg = <0x3d0000 0x10000>;
199 read-only;
200 };
201
202 partition@3e0000 {
203 label = "0:rpm";
204 reg = <0x3e0000 0x40000>;
205 read-only;
206 };
207
208 partition@420000 {
209 label = "0:rpm_1";
210 reg = <0x420000 0x40000>;
211 read-only;
212 };
213
214 partition@460000 {
215 label = "0:cdt";
216 reg = <0x460000 0x10000>;
217 read-only;
218 };
219
220 partition@470000 {
221 label = "0:cdt_1";
222 reg = <0x470000 0x10000>;
223 read-only;
224 };
225
226 partition@480000 {
227 label = "0:appsblenv";
228 reg = <0x480000 0x10000>;
229 };
230
231 partition@490000 {
232 label = "0:appsbl";
233 reg = <0x490000 0xa0000>;
234 read-only;
235 };
236
237 partition@530000 {
238 label = "0:appsbl_1";
239 reg = <0x530000 0xa0000>;
240 read-only;
241 };
242
243 partition@5d0000 {
244 label = "0:art";
245 reg = <0x5d0000 0x40000>;
246 read-only;
247 };
248
249 partition@610000 {
250 label = "0:ethphyfw";
251 reg = <0x610000 0x80000>;
252 read-only;
253 };
254 };
255 };
256 };
257
258 &blsp1_uart5 {
259 status = "okay";
260 };
261
262 &cryptobam {
263 status = "okay";
264 };
265
266 &crypto {
267 status = "okay";
268 };
269
270 &prng {
271 status = "okay";
272 };
273
274 &qpic_bam {
275 status = "okay";
276 };
277
278 &qpic_nand {
279 status = "okay";
280
281 partitions {
282 status = "disabled";
283 };
284
285 nand@0 {
286 reg = <0>;
287 nand-ecc-strength = <8>;
288 nand-ecc-step-size = <512>;
289 nand-bus-width = <8>;
290
291 partitions {
292 compatible = "fixed-partitions";
293 #address-cells = <1>;
294 #size-cells = <1>;
295
296 partition@0 {
297 label = "rootfs";
298 reg = <0x0000000 0x3400000>;
299 };
300
301 partition@3400000 {
302 label = "0:wififw";
303 reg = <0x3400000 0x0800000>;
304 read-only;
305 };
306
307 partition@3c00000 {
308 label = "rootfs_1";
309 reg = <0x3c00000 0x3400000>;
310 };
311
312 partition@7000000 {
313 label = "0:wififw_1";
314 reg = <0x7000000 0x0800000>;
315 read-only;
316 };
317 };
318 };
319 };
320
321 &qusb_phy_0 {
322 status = "okay";
323 };
324
325 &qusb_phy_1 {
326 status = "okay";
327 };
328
329 &ssphy_0 {
330 status = "okay";
331 };
332
333 &ssphy_1 {
334 status = "okay";
335 };
336
337 &usb_0 {
338 status = "okay";
339 };
340
341 &usb_1 {
342 status = "okay";
343 };
344
345 &mdio {
346 status = "okay";
347
348 pinctrl-0 = <&mdio_pins>;
349 pinctrl-names = "default";
350 reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
351
352 ethernet-phy-package@0 {
353 compatible = "qcom,qca8075-package";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 reg = <0>;
357
358 qca8075_0: ethernet-phy@0 {
359 compatible = "ethernet-phy-ieee802.3-c22";
360 reg = <0>;
361 };
362
363 qca8075_1: ethernet-phy@1 {
364 compatible = "ethernet-phy-ieee802.3-c22";
365 reg = <1>;
366 };
367
368 qca8075_2: ethernet-phy@2 {
369 compatible = "ethernet-phy-ieee802.3-c22";
370 reg = <2>;
371 };
372
373 qca8075_3: ethernet-phy@3 {
374 compatible = "ethernet-phy-ieee802.3-c22";
375 reg = <3>;
376 };
377
378 qca8075_4: ethernet-phy@4 {
379 compatible = "ethernet-phy-ieee802.3-c22";
380 reg = <4>;
381 };
382 };
383 };
384
385 &switch {
386 status = "okay";
387
388 switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
389 switch_wan_bmp = <ESS_PORT5>;
390 switch_mac_mode = <MAC_MODE_PSGMII>;
391
392 qcom,port_phyinfo {
393 port@1 {
394 port_id = <1>;
395 phy_address = <0>;
396 };
397 port@2 {
398 port_id = <2>;
399 phy_address = <1>;
400 };
401 port@3 {
402 port_id = <3>;
403 phy_address = <2>;
404 };
405 port@4 {
406 port_id = <4>;
407 phy_address = <3>;
408 };
409 port@5 {
410 port_id = <5>;
411 phy_address = <4>;
412 };
413 };
414 };
415
416 &edma {
417 status = "okay";
418 };
419
420 &dp1 {
421 status = "okay";
422 phy-handle = <&qca8075_0>;
423 label = "lan1";
424 };
425
426 &dp2 {
427 status = "okay";
428 phy-handle = <&qca8075_1>;
429 label = "lan2";
430 };
431
432 &dp3 {
433 status = "okay";
434 phy-handle = <&qca8075_2>;
435 label = "lan3";
436 };
437
438 &dp4 {
439 status = "okay";
440 phy-handle = <&qca8075_3>;
441 label = "lan4";
442 };
443
444 &dp5 {
445 status = "okay";
446 phy-handle = <&qca8075_4>;
447 label = "wan";
448 };
449
450 &wifi {
451 status = "okay";
452
453 qcom,ath11k-calibration-variant = "ZBT-Z800AX";
454 };