f3d2fa34126470e421373ccec0e778c06fd9156b
[openwrt/staging/stintel.git] / target / linux / qualcommax / files / arch / arm64 / boot / dts / qcom / ipq8071-eap102.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* Copyright (c) 2022, Matthew Hagan <mnhagan88@gmail.com> */
3
4 /dts-v1/;
5
6 #include "ipq8074.dtsi"
7 #include "ipq8074-ac-cpu.dtsi"
8 #include "ipq8074-ess.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12
13 / {
14 model = "Edgecore EAP102";
15 compatible = "edgecore,eap102", "qcom,ipq8074";
16
17 aliases {
18 serial0 = &blsp1_uart5;
19 serial1 = &blsp1_uart3;
20 led-boot = &led_system_green;
21 led-failsafe = &led_system_green;
22 led-running = &led_system_green;
23 led-upgrade = &led_system_green;
24 /* Aliases as required by u-boot to patch MAC addresses */
25 ethernet0 = &dp6;
26 ethernet1 = &dp5;
27 label-mac-device = &dp5;
28 };
29
30 chosen {
31 stdout-path = "serial0:115200n8";
32 bootargs-append = " root=/dev/ubiblock0_1";
33 };
34
35 keys {
36 compatible = "gpio-keys";
37 pinctrl-0 = <&button_pins>;
38 pinctrl-names = "default";
39
40 reset {
41 label = "reset";
42 gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
43 linux,code = <KEY_RESTART>;
44 };
45 };
46
47 leds {
48 compatible = "gpio-leds";
49
50 led_wanpoe {
51 label = "green:wanpoe";
52 gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
53 };
54
55 led_wlan2g {
56 label = "green:wlan2g";
57 gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
58 linux,default-trigger = "phy1radio";
59 };
60
61 led_wlan5g {
62 label = "green:wlan5g";
63 gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "phy0radio";
65 };
66
67 led_system_green: led_system {
68 function = LED_FUNCTION_POWER;
69 color = <LED_COLOR_ID_GREEN>;
70 gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
71 };
72 };
73 };
74
75 &tlmm {
76 mdio_pins: mdio-pins {
77 mdc {
78 pins = "gpio68";
79 function = "mdc";
80 drive-strength = <8>;
81 bias-pull-up;
82 };
83
84 mdio {
85 pins = "gpio69";
86 function = "mdio";
87 drive-strength = <8>;
88 bias-pull-up;
89 };
90 };
91
92 button_pins: button_pins {
93 reset_button {
94 pins = "gpio66";
95 function = "gpio";
96 drive-strength = <8>;
97 bias-pull-up;
98 };
99 };
100 };
101
102 &blsp1_spi1 {
103 status = "okay";
104
105 flash@0 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0>;
109 compatible = "jedec,spi-nor";
110 spi-max-frequency = <50000000>;
111
112 partitions {
113 compatible = "fixed-partitions";
114 #address-cells = <1>;
115 #size-cells = <1>;
116
117 partition@0 {
118 label = "0:sbl1";
119 reg = <0x0 0x50000>;
120 read-only;
121 };
122
123 partition@50000 {
124 label = "0:mibib";
125 reg = <0x50000 0x10000>;
126 read-only;
127 };
128
129 partition@60000 {
130 label = "0:bootconfig";
131 reg = <0x60000 0x20000>;
132 read-only;
133 };
134
135 partition@80000 {
136 label = "0:bootconfig1";
137 reg = <0x80000 0x20000>;
138 read-only;
139 };
140
141 partition@a0000 {
142 label = "0:qsee";
143 reg = <0xa0000 0x180000>;
144 read-only;
145 };
146
147 partition@220000 {
148 label = "0:qsee_1";
149 reg = <0x220000 0x180000>;
150 read-only;
151 };
152
153 partition@3a0000 {
154 label = "0:devcfg";
155 reg = <0x3a0000 0x10000>;
156 read-only;
157 };
158
159 partition@3b0000 {
160 label = "0:devcfg_1";
161 reg = <0x3b0000 0x10000>;
162 read-only;
163 };
164
165 partition@3c0000 {
166 label = "0:apdp";
167 reg = <0x3c0000 0x10000>;
168 read-only;
169 };
170
171 partition@3d0000 {
172 label = "0:apdp_1";
173 reg = <0x3d0000 0x10000>;
174 read-only;
175 };
176
177 partition@3e0000 {
178 label = "0:rpm";
179 reg = <0x3e0000 0x40000>;
180 read-only;
181 };
182
183 partition@420000 {
184 label = "0:rpm_1";
185 reg = <0x420000 0x40000>;
186 read-only;
187 };
188
189 partition@460000 {
190 label = "0:cdt";
191 reg = <0x460000 0x10000>;
192 read-only;
193 };
194
195 partition@470000 {
196 label = "0:cdt_1";
197 reg = <0x470000 0x10000>;
198 read-only;
199 };
200
201 partition@480000 {
202 label = "0:appsblenv";
203 reg = <0x480000 0x10000>;
204 };
205
206 partition@490000 {
207 label = "0:appsbl";
208 reg = <0x490000 0xc0000>;
209 read-only;
210 };
211
212 partition@550000 {
213 label = "0:appsbl_1";
214 reg = <0x530000 0xc0000>;
215 read-only;
216 };
217
218 partition@610000 {
219 label = "0:art";
220 reg = <0x610000 0x40000>;
221 read-only;
222 };
223
224 partition@650000 {
225 label = "0:ethphyfw";
226 reg = <0x650000 0x80000>;
227 read-only;
228 };
229
230 partition@6d0000 {
231 label = "0:product_info";
232 reg = <0x6d0000 0x80000>;
233 read-only;
234 };
235
236 partition@750000 {
237 label = "priv_data1";
238 reg = <0x750000 0x10000>;
239 read-only;
240 };
241
242 partition@760000 {
243 label = "priv_data2";
244 reg = <0x760000 0x10000>;
245 read-only;
246 };
247 };
248 };
249 };
250
251 &blsp1_uart3 {
252 status = "okay";
253 };
254
255 &blsp1_uart5 {
256 status = "okay";
257 };
258
259 &crypto {
260 status = "okay";
261 };
262
263 &cryptobam {
264 status = "okay";
265 };
266
267 &prng {
268 status = "okay";
269 };
270
271 &qpic_bam {
272 status = "okay";
273 };
274
275 &qusb_phy_0 {
276 status = "okay";
277 };
278
279 &ssphy_0 {
280 status = "okay";
281 };
282
283 &usb_0 {
284 status = "okay";
285 };
286
287 &qpic_nand {
288 status = "okay";
289
290 nand@0 {
291 reg = <0>;
292 nand-ecc-strength = <8>;
293 nand-ecc-step-size = <512>;
294 nand-bus-width = <8>;
295
296 partitions {
297 compatible = "fixed-partitions";
298 #address-cells = <1>;
299 #size-cells = <1>;
300
301 partition@0 {
302 label = "rootfs1";
303 reg = <0x0000000 0x3400000>;
304 };
305
306 partition@3400000 {
307 label = "0:wififw";
308 reg = <0x3400000 0x800000>;
309 read-only;
310 };
311
312 partition@3c00000 {
313 label = "rootfs2";
314 reg = <0x3c00000 0x3400000>;
315 };
316
317 partition@7000000 {
318 label = "0:wififw_1";
319 reg = <0x7000000 0x800000>;
320 read-only;
321 };
322 };
323 };
324 };
325
326 &mdio {
327 status = "okay";
328
329 pinctrl-0 = <&mdio_pins>;
330 pinctrl-names = "default";
331
332 qca8081_24: ethernet-phy@24 {
333 compatible = "ethernet-phy-id004d.d101";
334 reg = <24>;
335 reset-deassert-us = <10000>;
336 reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
337 };
338
339 qca8081_28: ethernet-phy@28 {
340 compatible = "ethernet-phy-id004d.d101";
341 reg = <28>;
342 reset-deassert-us = <10000>;
343 reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
344 };
345 };
346
347 &switch {
348 status = "okay";
349
350 switch_lan_bmp = <ESS_PORT5>; /* lan port bitmap */
351 switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
352 switch_mac_mode1 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance1*/
353 switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance2*/
354
355 qcom,port_phyinfo {
356 port@5 {
357 port_id = <5>;
358 phy_address = <24>;
359 port_mac_sel = "QGMAC_PORT";
360 };
361 port@6 {
362 port_id = <6>;
363 phy_address = <28>;
364 port_mac_sel = "QGMAC_PORT";
365 };
366 };
367 };
368
369 &edma {
370 status = "okay";
371 };
372
373 &dp5 {
374 status = "okay";
375 phy-handle = <&qca8081_24>;
376 label = "lan";
377 };
378
379 &dp6 {
380 status = "okay";
381 phy-handle = <&qca8081_28>;
382 label = "wan";
383 };
384
385 &wifi {
386 status = "okay";
387
388 qcom,ath11k-calibration-variant = "Edgecore-EAP102";
389 };