target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9132-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9 #include "puzzle-thermal.dtsi"
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/input/input.h>
  13 #include <dt-bindings/leds/common.h>
  14
  15 / {
  16         model = "iEi Puzzle-M902";
  17         compatible = "iei,puzzle-m902",
  18                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  19
  20         chosen {
  21                 stdout-path = "serial0:115200n8";
  22         };
  23
  24         aliases {
  25                 i2c0 = &cp1_i2c0;
  26                 i2c1 = &cp0_i2c0;
  27                 gpio1 = &cp0_gpio1;
  28                 gpio2 = &cp0_gpio2;
  29                 gpio3 = &cp1_gpio1;
  30                 gpio4 = &cp1_gpio2;
  31                 gpio5 = &cp2_gpio1;
  32                 gpio6 = &cp2_gpio2;
  33                 ethernet0 = &cp0_eth0;
  34                 ethernet1 = &cp0_eth1;
  35                 ethernet2 = &cp0_eth2;
  36                 ethernet3 = &cp1_eth0;
  37                 ethernet4 = &cp1_eth1;
  38                 ethernet5 = &cp1_eth2;
  39                 ethernet6 = &cp2_eth0;
  40                 ethernet7 = &cp2_eth1;
  41                 ethernet8 = &cp2_eth2;
  42                 spi1 = &cp0_spi0;
  43                 spi2 = &cp0_spi1;
  44                 led-boot = &led_power;
  45                 led-failsafe = &led_info;
  46                 led-running = &led_power;
  47                 led-upgrade = &led_info;
  48         };
  49
  50         memory@00000000 {
  51                 device_type = "memory";
  52                 reg = <0x0 0x0 0x0 0x80000000>;
  53         };
  54
  55         gpio_keys {
  56                 compatible = "gpio-keys";
  57
  58                 reset {
  59                         label = "Reset";
  60                         linux,code = <KEY_RESTART>;
  61                         gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
  62                 };
  63         };
  64
  65         cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "cp2-xhci0-vbus";
  68                 regulator-min-microvolt = <5000000>;
  69                 regulator-max-microvolt = <5000000>;
  70                 enable-active-high;
  71                 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
  72         };
  73
  74         cp2_usb3_0_phy0: cp2_usb3_phy0 {
  75                 compatible = "usb-nop-xceiv";
  76                 vcc-supply = <&cp2_reg_usb3_vbus0>;
  77         };
  78
  79         cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "cp2-xhci1-vbus";
  82                 regulator-min-microvolt = <5000000>;
  83                 regulator-max-microvolt = <5000000>;
  84                 enable-active-high;
  85                 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
  86         };
  87
  88         cp2_usb3_0_phy1: cp2_usb3_phy1 {
  89                 compatible = "usb-nop-xceiv";
  90                 vcc-supply = <&cp2_reg_usb3_vbus1>;
  91         };
  92
  93         cp2_sfp_eth0: sfp-eth0 {
  94                 compatible = "sff,sfp";
  95                 i2c-bus = <&cp2_sfpp0_i2c>;
  96                 los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
  97                 mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
  98                 tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
  99                 tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
 100                 status = "disabled";
 101         };
 102 };
 103
 104 &uart0 {
 105         status = "okay";
 106 };
 107
 108 &cp0_uart0 {
 109         status = "okay";
 110
 111         puzzle-mcu {
 112                 compatible = "iei,wt61p803-puzzle";
 113                 #address-cells = <1>;
 114                 #size-cells = <1>;
 115                 current-speed = <115200>;
 116                 enable-beep;
 117                 status = "okay";
 118
 119                 leds {
 120                         compatible = "iei,wt61p803-puzzle-leds";
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123                         status = "okay";
 124
 125                         led@0 {
 126                                 reg = <0>;
 127                                 label = "white:network";
 128                                 active-low;
 129                         };
 130
 131                         led@1 {
 132                                 reg = <1>;
 133                                 label = "green:cloud";
 134                                 active-low;
 135                         };
 136
 137                         led_info: led@2 {
 138                                 reg = <2>;
 139                                 label = "orange:info";
 140                                 active-low;
 141                         };
 142
 143                         led_power: led@3 {
 144                                 reg = <3>;
 145                                 function = LED_FUNCTION_POWER;
 146                                 color = <LED_COLOR_ID_YELLOW>;
 147                                 active-low;
 148                                 default-state = "on";
 149                         };
 150                 };
 151
 152                 hwmon {
 153                         compatible = "iei,wt61p803-puzzle-hwmon";
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156
 157                         chassis_fan_group0: fan-group@0 {
 158                                 #cooling-cells = <2>;
 159                                 reg = <0x00>;
 160                                 cooling-levels = <0 159 195 211 223 241 255>;
 161                         };
 162                 };
 163         };
 164 };
 165
 166 &ap_thermal_ic {
 167         PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
 168 };
 169
 170 &cp0_thermal_ic {
 171         PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
 172 };
 173
 174
 175 /* on-board eMMC - U9 */
 176 &ap_sdhci0 {
 177         pinctrl-names = "default";
 178         bus-width = <8>;
 179         status = "okay";
 180         mmc-ddr-1_8v;
 181         mmc-hs400-1_8v;
 182 };
 183
 184 &cp0_crypto {
 185         status = "okay";
 186 };
 187
 188 &cp0_xmdio {
 189         status = "okay";
 190         cp0_nbaset_phy0: ethernet-phy@0 {
 191                 compatible = "ethernet-phy-ieee802.3-c45";
 192                 reg = <2>;
 193         };
 194         cp0_nbaset_phy1: ethernet-phy@1 {
 195                 compatible = "ethernet-phy-ieee802.3-c45";
 196                 reg = <0>;
 197         };
 198         cp0_nbaset_phy2: ethernet-phy@2 {
 199                 compatible = "ethernet-phy-ieee802.3-c45";
 200                 reg = <8>;
 201         };
 202 };
 203
 204 &cp0_ethernet {
 205         status = "okay";
 206 };
 207
 208 /* SLM-1521-V2, CON9 */
 209 &cp0_eth0 {
 210         status = "okay";
 211         phy-mode = "10gbase-kr";
 212         phys = <&cp0_comphy2 0>;
 213         phy = <&cp0_nbaset_phy0>;
 214 };
 215
 216 &cp0_eth1 {
 217         status = "okay";
 218         phy-mode = "2500base-x";
 219         phys = <&cp0_comphy4 1>;
 220         phy = <&cp0_nbaset_phy1>;
 221 };
 222
 223 &cp0_eth2 {
 224         status = "okay";
 225         phy-mode = "2500base-x";
 226         phys = <&cp0_comphy1 2>;
 227         phy = <&cp0_nbaset_phy2>;
 228 };
 229
 230 &cp0_gpio1 {
 231         status = "okay";
 232 };
 233
 234 &cp0_gpio2 {
 235         status = "okay";
 236 };
 237
 238 &cp0_i2c0 {
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&cp0_i2c0_pins>;
 241         status = "okay";
 242         clock-frequency = <100000>;
 243         rtc@32 {
 244                 compatible = "epson,rx8130";
 245                 reg = <0x32>;
 246                 wakeup-source;
 247         };
 248 };
 249
 250 &cp0_i2c1 {
 251         clock-frequency = <100000>;
 252 };
 253
 254 /* SLM-1521-V2, CON6 */
 255 &cp0_sata0 {
 256         status = "okay";
 257         sata-port@1 {
 258                 status = "okay";
 259                 phys = <&cp0_comphy0 1>;
 260         };
 261 };
 262
 263 &cp0_pcie2 {
 264         status = "okay";
 265         num-lanes = <1>;
 266         num-viewport = <8>;
 267         phys = <&cp0_comphy5 2>;
 268 };
 269
 270 /* U55 */
 271 &cp0_spi1 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&cp0_spi0_pins>;
 274         reg = <0x700680 0x50>,          /* control */
 275               <0x2000000 0x1000000>;    /* CS0 */
 276         status = "okay";
 277         spi-flash@0 {
 278                 #address-cells = <0x1>;
 279                 #size-cells = <0x1>;
 280                 compatible = "jedec,spi-nor";
 281                 reg = <0x0>;
 282                 spi-max-frequency = <40000000>;
 283                 partitions {
 284                         compatible = "fixed-partitions";
 285                         #address-cells = <1>;
 286                         #size-cells = <1>;
 287                         partition@0 {
 288                                 label = "U-Boot";
 289                                 reg = <0x0 0x1f0000>;
 290                         };
 291                         partition@1f0000 {
 292                                 label = "U-Boot ENV Factory";
 293                                 reg = <0x1f0000 0x10000>;
 294                         };
 295                         partition@200000 {
 296                                 label = "Reserved";
 297                                 reg = <0x200000 0x1f0000>;
 298                         };
 299                         partition@3f0000 {
 300                                 label = "U-Boot ENV";
 301                                 reg = <0x3f0000 0x10000>;
 302                         };
 303                 };
 304         };
 305 };
 306
 307 &cp0_rtc {
 308         status = "disabled";
 309 };
 310
 311 &cp0_syscon0 {
 312         cp0_pinctrl: pinctrl {
 313                 compatible = "marvell,cp115-standalone-pinctrl";
 314                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 315                         marvell,pins = "mpp37", "mpp38";
 316                         marvell,function = "i2c0";
 317                 };
 318                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 319                         marvell,pins = "mpp35", "mpp36";
 320                         marvell,function = "i2c1";
 321                 };
 322                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 323                         marvell,pins = "mpp0", "mpp1", "mpp2",
 324                                        "mpp3", "mpp4", "mpp5",
 325                                        "mpp6", "mpp7", "mpp8",
 326                                        "mpp9", "mpp10", "mpp11";
 327                         marvell,function = "ge0";
 328                 };
 329                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 330                         marvell,pins = "mpp44", "mpp45", "mpp46",
 331                                        "mpp47", "mpp48", "mpp49",
 332                                        "mpp50", "mpp51", "mpp52",
 333                                        "mpp53", "mpp54", "mpp55";
 334                         marvell,function = "ge1";
 335                 };
 336                 cp0_spi0_pins: cp0-spi-pins-0 {
 337                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 338                         marvell,function = "spi1";
 339                 };
 340         };
 341 };
 342
 343 &cp0_usb3_1 {
 344         status = "okay";
 345         phys = <&cp0_comphy3 1>;
 346         phy-names = "usb";
 347 };
 348
 349 /*
 350  * Instantiate the first connected CP115
 351  */
 352
 353 #define CP11X_NAME              cp1
 354 #define CP11X_BASE              f4000000
 355 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
 356 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 357 #define CP11X_PCIE0_BASE        f4600000
 358 #define CP11X_PCIE1_BASE        f4620000
 359 #define CP11X_PCIE2_BASE        f4640000
 360
 361 #include "armada-cp115.dtsi"
 362
 363 #undef CP11X_NAME
 364 #undef CP11X_BASE
 365 #undef CP11X_PCIEx_MEM_BASE
 366 #undef CP11X_PCIEx_MEM_SIZE
 367 #undef CP11X_PCIE0_BASE
 368 #undef CP11X_PCIE1_BASE
 369 #undef CP11X_PCIE2_BASE
 370
 371 &cp1_crypto {
 372         status = "okay";
 373 };
 374
 375 &cp1_xmdio {
 376         status = "okay";
 377         cp1_nbaset_phy0: ethernet-phy@3 {
 378                 compatible = "ethernet-phy-ieee802.3-c45";
 379                 reg = <2>;
 380         };
 381         cp1_nbaset_phy1: ethernet-phy@4 {
 382                 compatible = "ethernet-phy-ieee802.3-c45";
 383                 reg = <0>;
 384         };
 385         cp1_nbaset_phy2: ethernet-phy@5 {
 386                 compatible = "ethernet-phy-ieee802.3-c45";
 387                 reg = <8>;
 388         };
 389 };
 390
 391 &cp1_ethernet {
 392         status = "okay";
 393 };
 394
 395 /* CON50 */
 396 &cp1_eth0 {
 397         status = "okay";
 398         phy-mode = "10gbase-kr";
 399         phys = <&cp1_comphy2 0>;
 400         phy = <&cp1_nbaset_phy0>;
 401 };
 402
 403 &cp1_eth1 {
 404         status = "okay";
 405         phy-mode = "2500base-x";
 406         phys = <&cp1_comphy4 1>;
 407         phy = <&cp1_nbaset_phy1>;
 408 };
 409
 410 &cp1_eth2 {
 411         status = "okay";
 412         phy-mode = "2500base-x";
 413         phys = <&cp1_comphy1 2>;
 414         phy = <&cp1_nbaset_phy2>;
 415 };
 416
 417 &cp1_gpio1 {
 418         status = "okay";
 419 };
 420
 421 &cp1_gpio2 {
 422         status = "okay";
 423 };
 424
 425 &cp1_i2c0 {
 426         status = "okay";
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&cp1_i2c0_pins>;
 429         clock-frequency = <100000>;
 430 };
 431
 432 &cp1_rtc {
 433         status = "disabled";
 434 };
 435
 436 &cp1_syscon0 {
 437         cp1_pinctrl: pinctrl {
 438                 compatible = "marvell,cp115-standalone-pinctrl";
 439                 cp1_i2c0_pins: cp1-i2c-pins-0 {
 440                         marvell,pins = "mpp37", "mpp38";
 441                         marvell,function = "i2c0";
 442                 };
 443                 cp1_spi0_pins: cp1-spi-pins-0 {
 444                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 445                         marvell,function = "spi1";
 446                 };
 447                 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
 448                         marvell,pins = "mpp3";
 449                         marvell,function = "gpio";
 450                 };
 451         };
 452 };
 453
 454 &cp1_thermal_ic {
 455         PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
 456 };
 457
 458 /*
 459  * Instantiate the second connected CP115
 460  */
 461
 462 #define CP11X_NAME              cp2
 463 #define CP11X_BASE              f6000000
 464 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
 465 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 466 #define CP11X_PCIE0_BASE        f6600000
 467 #define CP11X_PCIE1_BASE        f6620000
 468 #define CP11X_PCIE2_BASE        f6640000
 469
 470 #include "armada-cp115.dtsi"
 471
 472 #undef CP11X_NAME
 473 #undef CP11X_BASE
 474 #undef CP11X_PCIEx_MEM_BASE
 475 #undef CP11X_PCIEx_MEM_SIZE
 476 #undef CP11X_PCIE0_BASE
 477 #undef CP11X_PCIE1_BASE
 478 #undef CP11X_PCIE2_BASE
 479
 480 &cp2_crypto {
 481         status = "okay";
 482 };
 483
 484 &cp2_ethernet {
 485         status = "okay";
 486 };
 487
 488 &cp2_xmdio {
 489         status = "okay";
 490         cp2_nbaset_phy0: ethernet-phy@6 {
 491                 compatible = "ethernet-phy-ieee802.3-c45";
 492                 reg = <2>;
 493         };
 494         cp2_nbaset_phy1: ethernet-phy@7 {
 495                 compatible = "ethernet-phy-ieee802.3-c45";
 496                 reg = <0>;
 497         };
 498         cp2_nbaset_phy2: ethernet-phy@8 {
 499                 compatible = "ethernet-phy-ieee802.3-c45";
 500                 reg = <8>;
 501         };
 502 };
 503
 504 /* SLM-1521-V2, CON9 */
 505 &cp2_eth0 {
 506         status = "okay";
 507         phy-mode = "10gbase-kr";
 508         phys = <&cp2_comphy2 0>;
 509         phy = <&cp2_nbaset_phy0>;
 510 };
 511
 512 &cp2_eth1 {
 513         status = "okay";
 514         phy-mode = "2500base-x";
 515         phys = <&cp2_comphy4 1>;
 516         phy = <&cp2_nbaset_phy1>;
 517 };
 518
 519 &cp2_eth2 {
 520         status = "okay";
 521         phy-mode = "2500base-x";
 522         phys = <&cp2_comphy1 2>;
 523         phy = <&cp2_nbaset_phy2>;
 524 };
 525
 526 &cp2_gpio1 {
 527         status = "okay";
 528 };
 529
 530 &cp2_gpio2 {
 531         status = "okay";
 532 };
 533
 534 &cp2_i2c0 {
 535         clock-frequency = <100000>;
 536         /* SLM-1521-V2 - U3 */
 537         i2c-mux@72 {
 538                 compatible = "nxp,pca9544";
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 reg = <0x72>;
 542                 cp2_sfpp0_i2c: i2c@0 {
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         reg = <0>;
 546                 };
 547
 548                 i2c@1 {
 549                         #address-cells = <1>;
 550                         #size-cells = <0>;
 551                         reg = <1>;
 552                         /* U12 */
 553                         cp2_module_expander1: pca9555@21 {
 554                                 compatible = "nxp,pca9555";
 555                                 pinctrl-names = "default";
 556                                 gpio-controller;
 557                                 #gpio-cells = <2>;
 558                                 reg = <0x21>;
 559                         };
 560                 };
 561         };
 562 };
 563
 564 &cp2_rtc {
 565         status = "disabled";
 566 };
 567
 568 &cp2_syscon0 {
 569         cp2_pinctrl: pinctrl {
 570                 compatible = "marvell,cp115-standalone-pinctrl";
 571                 cp2_i2c0_pins: cp2-i2c-pins-0 {
 572                         marvell,pins = "mpp37", "mpp38";
 573                         marvell,function = "i2c0";
 574                 };
 575         };
 576 };
 577
 578 &cp2_thermal_ic {
 579         PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);
 580 };