d202d71c7f721d6ef535f6ffb3860f8e6318c052
[openwrt/staging/stintel.git] / target / linux / mvebu / files-6.1 / arch / arm / boot / dts / armada-385-fortinet-fg-50e.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "armada-385-fortinet-fg-x0e.dtsi"
4
5 / {
6 model = "Fortinet FortiGate 50E";
7 compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x80000000>; /* 2GB */
12 };
13 };
14
15 &gpio_leds {
16 led-14 {
17 gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
18 color = <LED_COLOR_ID_GREEN>;
19 linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
20 };
21
22 led-15 {
23 gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
24 color = <LED_COLOR_ID_GREEN>;
25 linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
26 };
27
28 led-16 {
29 gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
30 color = <LED_COLOR_ID_AMBER>;
31 linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
32 };
33
34 led-17 {
35 gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
36 color = <LED_COLOR_ID_GREEN>;
37 linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
38 };
39 };
40
41 &pinctrl {
42 pmx_phy_switch_pins: phy-switch-pins {
43 marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
44 marvell,function = "gpio";
45 };
46 };
47
48 &eth1 {
49 status = "okay";
50
51 phy-handle = <&ethphy0>;
52 phy-connection-type = "sgmii";
53 buffer-manager = <&bm>;
54 bm,pool-long = <2>;
55 nvmem-cells = <&macaddr_bdinfo_d880 1>;
56 nvmem-cell-names = "mac-address";
57 };
58
59 &eth2 {
60 status = "okay";
61
62 phy-handle = <&ethphy1>;
63 phy-connection-type = "sgmii";
64 buffer-manager = <&bm>;
65 bm,pool-long = <3>;
66 nvmem-cells = <&macaddr_bdinfo_d880 2>;
67 nvmem-cell-names = "mac-address";
68 };
69
70 &mdio {
71 pinctrl-names = "default";
72 pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
73
74 /* Marvell 88E1512 */
75 ethphy0: ethernet-phy@0 {
76 compatible = "ethernet-phy-id0141,0dd1",
77 "ethernet-phy-ieee802.3-c22";
78 reg = <0>;
79 interrupt-parent = <&gpio0>;
80 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
81 reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
82 reset-assert-us = <10000>;
83 reset-deassert-us = <10000>;
84 /*
85 * LINK/ACT (Green): LED[0], Active Low
86 * SPEED 100M (Amber): LED[1], Active High
87 */
88 marvell,reg-init = <3 16 0 0x71>,
89 <3 17 0 0x4>;
90 };
91
92 /* Marvell 88E1512 */
93 ethphy1: ethernet-phy@1 {
94 compatible = "ethernet-phy-id0141,0dd1",
95 "ethernet-phy-ieee802.3-c22";
96 reg = <1>;
97 interrupt-parent = <&gpio1>;
98 interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
99 reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
100 reset-assert-us = <10000>;
101 reset-deassert-us = <10000>;
102 /*
103 * LINK/ACT (Green): LED[0], Active Low
104 * SPEED 100M (Amber): LED[1], Active High
105 */
106 marvell,reg-init = <3 16 0 0x71>,
107 <3 17 0 0x4>;
108 };
109
110 /* Marvell 88E6176 */
111 switch@2 {
112 compatible = "marvell,mv88e6085";
113 reg = <0x2>;
114 reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
115
116 ports {
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 port@0 {
121 reg = <0>;
122 label = "lan5";
123 nvmem-cells = <&macaddr_bdinfo_d880 7>;
124 nvmem-cell-names = "mac-address";
125 };
126
127 port@1 {
128 reg = <1>;
129 label = "lan4";
130 nvmem-cells = <&macaddr_bdinfo_d880 6>;
131 nvmem-cell-names = "mac-address";
132 };
133
134 port@2 {
135 reg = <2>;
136 label = "lan3";
137 nvmem-cells = <&macaddr_bdinfo_d880 5>;
138 nvmem-cell-names = "mac-address";
139 };
140
141 port@3 {
142 reg = <3>;
143 label = "lan2";
144 nvmem-cells = <&macaddr_bdinfo_d880 4>;
145 nvmem-cell-names = "mac-address";
146 };
147
148 port@4 {
149 reg = <4>;
150 label = "lan1";
151 nvmem-cells = <&macaddr_bdinfo_d880 3>;
152 nvmem-cell-names = "mac-address";
153 };
154
155 port@6 {
156 reg = <6>;
157 ethernet = <&eth0>;
158 phy-connection-type = "rgmii-id";
159
160 fixed-link {
161 speed = <1000>;
162 full-duplex;
163 };
164 };
165 };
166 };
167 };