target/linux/mediatek/patches-6.6/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch

   1 From: Daniel Golle <daniel@makrotopia.org>
   2 Date: Tue, 10 Oct 2023 21:06:43 +0200
   3 Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of
   4  ADMAv2 on MT7981 and MT7986
   5
   6 ADMA is plagued by RX hangs which can't easily detected and happen upon
   7 receival of a corrupted package.
   8 Use QDMA just like on netsys v1 which is also still present and usable, and
   9 doesn't suffer from that problem.
  10
  11 Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
  12 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  13 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  14 ---
  15  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
  16  1 file changed, 23 insertions(+), 23 deletions(-)
  17
  18 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  19 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  20 @@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r
  21         .tx_irq_mask            = 0x461c,
  22         .tx_irq_status          = 0x4618,
  23         .pdma = {
  24 -               .rx_ptr         = 0x6100,
  25 -               .rx_cnt_cfg     = 0x6104,
  26 -               .pcrx_ptr       = 0x6108,
  27 -               .glo_cfg        = 0x6204,
  28 -               .rst_idx        = 0x6208,
  29 -               .delay_irq      = 0x620c,
  30 -               .irq_status     = 0x6220,
  31 -               .irq_mask       = 0x6228,
  32 -               .adma_rx_dbg0   = 0x6238,
  33 -               .int_grp        = 0x6250,
  34 +               .rx_ptr         = 0x4100,
  35 +               .rx_cnt_cfg     = 0x4104,
  36 +               .pcrx_ptr       = 0x4108,
  37 +               .glo_cfg        = 0x4204,
  38 +               .rst_idx        = 0x4208,
  39 +               .delay_irq      = 0x420c,
  40 +               .irq_status     = 0x4220,
  41 +               .irq_mask       = 0x4228,
  42 +               .adma_rx_dbg0   = 0x4238,
  43 +               .int_grp        = 0x4250,
  44         },
  45         .qdma = {
  46                 .qtx_cfg        = 0x4400,
  47 @@ -1232,7 +1232,7 @@ static bool mtk_rx_get_desc(struct mtk_e
  48         rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
  49         rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
  50         rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
  51 -       if (mtk_is_netsys_v2_or_greater(eth)) {
  52 +       if (mtk_is_netsys_v3_or_greater(eth)) {
  53                 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
  54                 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
  55         }
  56 @@ -2184,7 +2184,7 @@ static int mtk_poll_rx(struct napi_struc
  57                         break;
  58
  59                 /* find out which mac the packet come from. values start at 1 */
  60 -               if (mtk_is_netsys_v2_or_greater(eth)) {
  61 +               if (mtk_is_netsys_v3_or_greater(eth)) {
  62                         u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
  63
  64                         switch (val) {
  65 @@ -2296,7 +2296,7 @@ static int mtk_poll_rx(struct napi_struc
  66                 skb->dev = netdev;
  67                 bytes += skb->len;
  68
  69 -               if (mtk_is_netsys_v2_or_greater(eth)) {
  70 +               if (mtk_is_netsys_v3_or_greater(eth)) {
  71                         reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
  72                         hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
  73                         if (hash != MTK_RXD5_FOE_ENTRY)
  74 @@ -2846,7 +2846,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  75
  76                 rxd->rxd3 = 0;
  77                 rxd->rxd4 = 0;
  78 -               if (mtk_is_netsys_v2_or_greater(eth)) {
  79 +               if (mtk_is_netsys_v3_or_greater(eth)) {
  80                         rxd->rxd5 = 0;
  81                         rxd->rxd6 = 0;
  82                         rxd->rxd7 = 0;
  83 @@ -4053,7 +4053,7 @@ static int mtk_hw_init(struct mtk_eth *e
  84         else
  85                 mtk_hw_reset(eth);
  86
  87 -       if (mtk_is_netsys_v2_or_greater(eth)) {
  88 +       if (mtk_is_netsys_v3_or_greater(eth)) {
  89                 /* Set FE to PDMAv2 if necessary */
  90                 val = mtk_r32(eth, MTK_FE_GLO_MISC);
  91                 mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
  92 @@ -5400,11 +5400,11 @@ static const struct mtk_soc_data mt7981_
  93                 .dma_len_offset = 8,
  94         },
  95         .rx = {
  96 -               .desc_size = sizeof(struct mtk_rx_dma_v2),
  97 -               .irq_done_mask = MTK_RX_DONE_INT_V2,
  98 +               .desc_size = sizeof(struct mtk_rx_dma),
  99 +               .irq_done_mask = MTK_RX_DONE_INT,
 100                 .dma_l4_valid = RX_DMA_L4_VALID_V2,
 101 -               .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
 102 -               .dma_len_offset = 8,
 103 +               .dma_max_len = MTK_TX_DMA_BUF_LEN,
 104 +               .dma_len_offset = 16,
 105         },
 106  };
 107
 108 @@ -5426,11 +5426,11 @@ static const struct mtk_soc_data mt7986_
 109                 .dma_len_offset = 8,
 110         },
 111         .rx = {
 112 -               .desc_size = sizeof(struct mtk_rx_dma_v2),
 113 -               .irq_done_mask = MTK_RX_DONE_INT_V2,
 114 +               .desc_size = sizeof(struct mtk_rx_dma),
 115 +               .irq_done_mask = MTK_RX_DONE_INT,
 116                 .dma_l4_valid = RX_DMA_L4_VALID_V2,
 117 -               .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
 118 -               .dma_len_offset = 8,
 119 +               .dma_max_len = MTK_TX_DMA_BUF_LEN,
 120 +               .dma_len_offset = 16,
 121         },
 122  };
 123