target/linux/mediatek/patches-6.6/862-arm64-dts-mt7986-add-afe.patch

   1 From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
   2 From: Maso Huang <maso.huang@mediatek.com>
   3 Date: Thu, 7 Sep 2023 10:54:37 +0800
   4 Subject: [PATCH] arm64: dts: mt7986: add afe
   5
   6 ---
   7  arch/arm64/boot/dts/mediatek/mt7986a.dtsi     | 23 +++++++++++
   8  1 files changed, 23 insertions(+)
   9
  10 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
  11 +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
  12 @@ -248,6 +248,28 @@
  13                         status = "disabled";
  14                 };
  15
  16 +               afe: audio-controller@11210000 {
  17 +                       compatible = "mediatek,mt7986-afe";
  18 +                       reg = <0 0x11210000 0 0x9000>;
  19 +                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
  20 +                       clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
  21 +                                <&infracfg CLK_INFRA_AUD_26M_CK>,
  22 +                                <&infracfg CLK_INFRA_AUD_L_CK>,
  23 +                                <&infracfg CLK_INFRA_AUD_AUD_CK>,
  24 +                                <&infracfg CLK_INFRA_AUD_EG2_CK>;
  25 +                       clock-names = "aud_bus_ck",
  26 +                                     "aud_26m_ck",
  27 +                                     "aud_l_ck",
  28 +                                     "aud_aud_ck",
  29 +                                     "aud_eg2_ck";
  30 +                       assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
  31 +                                         <&topckgen CLK_TOP_AUD_L_SEL>,
  32 +                                         <&topckgen CLK_TOP_A_TUNER_SEL>;
  33 +                       assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
  34 +                                                <&apmixedsys CLK_APMIXED_APLL2>,
  35 +                                                <&topckgen CLK_TOP_APLL2_D4>;
  36 +               };
  37 +
  38                 pwm: pwm@10048000 {
  39                         compatible = "mediatek,mt7986-pwm";
  40                         reg = <0 0x10048000 0 0x1000>;