target/linux/mediatek/patches-6.6/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch

   1 From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001
   2 From: Frank Wunderlich <frank-w@public-files.de>
   3 Date: Fri, 22 Sep 2023 07:50:20 +0200
   4 Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988
   5  support
   6
   7 Add Support for Mediatek Filogic 880/MT7988 LVTS.
   8
   9 Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
  10 Tested-by: Daniel Golle <daniel@makrotopia.org>
  11 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
  12 Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de
  13 ---
  14  drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++
  15  1 file changed, 38 insertions(+)
  16
  17 --- a/drivers/thermal/mediatek/lvts_thermal.c
  18 +++ b/drivers/thermal/mediatek/lvts_thermal.c
  19 @@ -82,6 +82,8 @@
  20  #define LVTS_GOLDEN_TEMP_DEFAULT       50
  21  #define LVTS_COEFF_A_MT8195                    -250460
  22  #define LVTS_COEFF_B_MT8195                    250460
  23 +#define LVTS_COEFF_A_MT7988                    -204650
  24 +#define LVTS_COEFF_B_MT7988                    204650
  25
  26  #define LVTS_MSR_IMMEDIATE_MODE                0
  27  #define LVTS_MSR_FILTERED_MODE         1
  28 @@ -89,6 +91,7 @@
  29  #define LVTS_MSR_READ_TIMEOUT_US       400
  30  #define LVTS_MSR_READ_WAIT_US          (LVTS_MSR_READ_TIMEOUT_US / 2)
  31
  32 +#define LVTS_HW_SHUTDOWN_MT7988                105000
  33  #define LVTS_HW_SHUTDOWN_MT8195                105000
  34
  35  #define LVTS_MINIMUM_THRESHOLD         20000
  36 @@ -1267,6 +1270,33 @@ static void lvts_remove(struct platform_
  37         lvts_debugfs_exit(lvts_td);
  38  }
  39
  40 +static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
  41 +       {
  42 +               .cal_offset = { 0x00, 0x04, 0x08, 0x0c },
  43 +               .lvts_sensor = {
  44 +                       { .dt_id = MT7988_CPU_0 },
  45 +                       { .dt_id = MT7988_CPU_1 },
  46 +                       { .dt_id = MT7988_ETH2P5G_0 },
  47 +                       { .dt_id = MT7988_ETH2P5G_1 }
  48 +               },
  49 +               .num_lvts_sensor = 4,
  50 +               .offset = 0x0,
  51 +               .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
  52 +       },
  53 +       {
  54 +               .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
  55 +               .lvts_sensor = {
  56 +                       { .dt_id = MT7988_TOPS_0},
  57 +                       { .dt_id = MT7988_TOPS_1},
  58 +                       { .dt_id = MT7988_ETHWARP_0},
  59 +                       { .dt_id = MT7988_ETHWARP_1}
  60 +               },
  61 +               .num_lvts_sensor = 4,
  62 +               .offset = 0x100,
  63 +               .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
  64 +       }
  65 +};
  66 +
  67  static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
  68         {
  69                 .cal_offset = { 0x04, 0x07 },
  70 @@ -1346,6 +1376,13 @@ static const struct lvts_ctrl_data mt819
  71         }
  72  };
  73
  74 +static const struct lvts_data mt7988_lvts_ap_data = {
  75 +       .lvts_ctrl      = mt7988_lvts_ap_data_ctrl,
  76 +       .num_lvts_ctrl  = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
  77 +       .temp_factor    = LVTS_COEFF_A_MT7988,
  78 +       .temp_offset    = LVTS_COEFF_B_MT7988,
  79 +};
  80 +
  81  static const struct lvts_data mt8195_lvts_mcu_data = {
  82         .lvts_ctrl      = mt8195_lvts_mcu_data_ctrl,
  83         .num_lvts_ctrl  = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
  84 @@ -1361,6 +1398,7 @@ static const struct lvts_data mt8195_lvt
  85  };
  86
  87  static const struct of_device_id lvts_of_match[] = {
  88 +       { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
  89         { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
  90         { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
  91         {},