target/linux/mediatek/patches-6.6/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch

   1 From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Sun, 17 Dec 2023 21:49:55 +0000
   4 Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
   5  MT7988
   6
   7 Add various clock controllers found in the MT7988 SoC to existing
   8 bindings (if applicable) and add files for the new ethwarp, mcusys
   9 and xfi-pll clock controllers not previously present in any SoC.
  10
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  13 Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
  14 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  .../arm/mediatek/mediatek,infracfg.yaml       |  1 +
  18  .../bindings/clock/mediatek,apmixedsys.yaml   |  1 +
  19  .../bindings/clock/mediatek,ethsys.yaml       |  1 +
  20  .../clock/mediatek,mt7988-ethwarp.yaml        | 52 +++++++++++++++
  21  .../clock/mediatek,mt7988-xfi-pll.yaml        | 48 ++++++++++++++
  22  .../bindings/clock/mediatek,topckgen.yaml     |  2 +
  23  .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 65 ++++++++++++++++---
  24  7 files changed, 161 insertions(+), 9 deletions(-)
  25  create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
  26  create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
  27
  28 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
  29 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
  30 @@ -30,6 +30,7 @@ properties:
  31                - mediatek,mt7629-infracfg
  32                - mediatek,mt7981-infracfg
  33                - mediatek,mt7986-infracfg
  34 +              - mediatek,mt7988-infracfg
  35                - mediatek,mt8135-infracfg
  36                - mediatek,mt8167-infracfg
  37                - mediatek,mt8173-infracfg
  38 --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
  39 +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
  40 @@ -22,6 +22,7 @@ properties:
  41            - mediatek,mt7622-apmixedsys
  42            - mediatek,mt7981-apmixedsys
  43            - mediatek,mt7986-apmixedsys
  44 +          - mediatek,mt7988-apmixedsys
  45            - mediatek,mt8135-apmixedsys
  46            - mediatek,mt8173-apmixedsys
  47            - mediatek,mt8516-apmixedsys
  48 --- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
  49 +++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
  50 @@ -22,6 +22,7 @@ properties:
  51                - mediatek,mt7629-ethsys
  52                - mediatek,mt7981-ethsys
  53                - mediatek,mt7986-ethsys
  54 +              - mediatek,mt7988-ethsys
  55            - const: syscon
  56        - items:
  57            - const: mediatek,mt7623-ethsys
  58 --- /dev/null
  59 +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
  60 @@ -0,0 +1,52 @@
  61 +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  62 +%YAML 1.2
  63 +---
  64 +$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
  65 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  66 +
  67 +title: MediaTek MT7988 ethwarp Controller
  68 +
  69 +maintainers:
  70 +  - Daniel Golle <daniel@makrotopia.org>
  71 +
  72 +description:
  73 +  The Mediatek MT7988 ethwarp controller provides clocks and resets for the
  74 +  Ethernet related subsystems found the MT7988 SoC.
  75 +  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
  76 +
  77 +properties:
  78 +  compatible:
  79 +    items:
  80 +      - const: mediatek,mt7988-ethwarp
  81 +
  82 +  reg:
  83 +    maxItems: 1
  84 +
  85 +  '#clock-cells':
  86 +    const: 1
  87 +
  88 +  '#reset-cells':
  89 +    const: 1
  90 +
  91 +required:
  92 +  - compatible
  93 +  - reg
  94 +  - '#clock-cells'
  95 +  - '#reset-cells'
  96 +
  97 +additionalProperties: false
  98 +
  99 +examples:
 100 +  - |
 101 +    #include <dt-bindings/reset/ti-syscon.h>
 102 +    soc {
 103 +        #address-cells = <2>;
 104 +        #size-cells = <2>;
 105 +
 106 +        clock-controller@15031000 {
 107 +            compatible = "mediatek,mt7988-ethwarp";
 108 +            reg = <0 0x15031000 0 0x1000>;
 109 +            #clock-cells = <1>;
 110 +            #reset-cells = <1>;
 111 +        };
 112 +    };
 113 --- /dev/null
 114 +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
 115 @@ -0,0 +1,48 @@
 116 +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 117 +%YAML 1.2
 118 +---
 119 +$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
 120 +$schema: http://devicetree.org/meta-schemas/core.yaml#
 121 +
 122 +title: MediaTek MT7988 XFI PLL Clock Controller
 123 +
 124 +maintainers:
 125 +  - Daniel Golle <daniel@makrotopia.org>
 126 +
 127 +description:
 128 +  The MediaTek XFI PLL controller provides the 156.25MHz clock for the
 129 +  Ethernet SerDes PHY from the 40MHz top_xtal clock.
 130 +
 131 +properties:
 132 +  compatible:
 133 +    const: mediatek,mt7988-xfi-pll
 134 +
 135 +  reg:
 136 +    maxItems: 1
 137 +
 138 +  resets:
 139 +    maxItems: 1
 140 +
 141 +  '#clock-cells':
 142 +    const: 1
 143 +
 144 +required:
 145 +  - compatible
 146 +  - reg
 147 +  - resets
 148 +  - '#clock-cells'
 149 +
 150 +additionalProperties: false
 151 +
 152 +examples:
 153 +  - |
 154 +    soc {
 155 +        #address-cells = <2>;
 156 +        #size-cells = <2>;
 157 +        clock-controller@11f40000 {
 158 +            compatible = "mediatek,mt7988-xfi-pll";
 159 +            reg = <0 0x11f40000 0 0x1000>;
 160 +            resets = <&watchdog 16>;
 161 +            #clock-cells = <1>;
 162 +        };
 163 +    };
 164 --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
 165 +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
 166 @@ -37,6 +37,8 @@ properties:
 167                - mediatek,mt7629-topckgen
 168                - mediatek,mt7981-topckgen
 169                - mediatek,mt7986-topckgen
 170 +              - mediatek,mt7988-mcusys
 171 +              - mediatek,mt7988-topckgen
 172                - mediatek,mt8167-topckgen
 173                - mediatek,mt8183-topckgen
 174            - const: syscon
 175 --- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
 176 +++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
 177 @@ -15,15 +15,22 @@ description:
 178
 179  properties:
 180    compatible:
 181 -    items:
 182 -      - enum:
 183 -          - mediatek,mt7622-sgmiisys
 184 -          - mediatek,mt7629-sgmiisys
 185 -          - mediatek,mt7981-sgmiisys_0
 186 -          - mediatek,mt7981-sgmiisys_1
 187 -          - mediatek,mt7986-sgmiisys_0
 188 -          - mediatek,mt7986-sgmiisys_1
 189 -      - const: syscon
 190 +    oneOf:
 191 +      - items:
 192 +          - enum:
 193 +              - mediatek,mt7622-sgmiisys
 194 +              - mediatek,mt7629-sgmiisys
 195 +              - mediatek,mt7981-sgmiisys_0
 196 +              - mediatek,mt7981-sgmiisys_1
 197 +              - mediatek,mt7986-sgmiisys_0
 198 +              - mediatek,mt7986-sgmiisys_1
 199 +          - const: syscon
 200 +      - items:
 201 +          - enum:
 202 +              - mediatek,mt7988-sgmiisys0
 203 +              - mediatek,mt7988-sgmiisys1
 204 +          - const: simple-mfd
 205 +          - const: syscon
 206
 207    reg:
 208      maxItems: 1
 209 @@ -35,11 +42,51 @@ properties:
 210      description: Invert polarity of the SGMII data lanes
 211      type: boolean
 212
 213 +  pcs:
 214 +    type: object
 215 +    description: MediaTek LynxI HSGMII PCS
 216 +    properties:
 217 +      compatible:
 218 +        const: mediatek,mt7988-sgmii
 219 +
 220 +      clocks:
 221 +        maxItems: 3
 222 +
 223 +      clock-names:
 224 +        items:
 225 +          - const: sgmii_sel
 226 +          - const: sgmii_tx
 227 +          - const: sgmii_rx
 228 +
 229 +    required:
 230 +      - compatible
 231 +      - clocks
 232 +      - clock-names
 233 +
 234 +    additionalProperties: false
 235 +
 236  required:
 237    - compatible
 238    - reg
 239    - '#clock-cells'
 240
 241 +allOf:
 242 +  - if:
 243 +      properties:
 244 +        compatible:
 245 +          contains:
 246 +            enum:
 247 +              - mediatek,mt7988-sgmiisys0
 248 +              - mediatek,mt7988-sgmiisys1
 249 +
 250 +    then:
 251 +      required:
 252 +        - pcs
 253 +
 254 +    else:
 255 +      properties:
 256 +        pcs: false
 257 +
 258  additionalProperties: false
 259
 260  examples: