target/linux/mediatek/patches-6.6/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch

   1 From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Sun, 18 Feb 2024 01:59:59 +0000
   4 Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
   5
   6 Without the SGM_REG_SEL clock enabled the system freezes if trying to
   7 access registers used by MT7981 clock drivers itself.
   8 Mark SGM_REG_SEL as critical to make sure it is always enabled to
   9 prevent freezes on boot depending on probe order.
  10
  11 Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support")
  12 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  13 ---
  14  drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++--
  15  1 file changed, 3 insertions(+), 2 deletions(-)
  16
  17 --- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
  18 +++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
  19 @@ -359,8 +359,9 @@ static const struct mtk_mux top_muxes[]
  20         MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
  21                              sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
  22                              0x1C0, 21),
  23 -       MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
  24 -                            0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
  25 +       MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
  26 +                                  0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
  27 +                                  CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
  28         MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
  29                              0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
  30         /* CLK_CFG_6 */