projects / openwrt / staging / stintel.git / blob
? search:


f9dd94a78a51a833e6e676f81674ca6eb2b58332
[openwrt/staging/stintel.git] / target / linux / mediatek / patches-6.6 / 231-v6.4-clk-mediatek-add-MT7981-clock-support.patch
1 From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Thu, 26 Jan 2023 03:34:24 +0000
4 Subject: [PATCH] clk: mediatek: add MT7981 clock support
5
6 Add MT7981 clock support, include topckgen, apmixedsys, infracfg and
7 ethernet subsystem clocks.
8
9 The drivers are based on clk-mt7981.c which can be found in MediaTek's
10 SDK sources. To be fit for upstream inclusion the driver has been split
11 into clock domains and the infracfg part has been significantly
12 de-bloated by removing all the 1:1 factors (aliases).
13
14 Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
15 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
16 Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org
17 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
18 [sboyd@kernel.org: Add module license]
19 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
20 ---
21 drivers/clk/mediatek/Kconfig | 17 +
22 drivers/clk/mediatek/Makefile | 4 +
23 drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 +++++
24 drivers/clk/mediatek/clk-mt7981-eth.c | 118 ++++++
25 drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++
26 drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++
27 6 files changed, 870 insertions(+)
28 create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c
29 create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c
30 create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c
31 create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c
32
33 --- a/drivers/clk/mediatek/Kconfig
34 +++ b/drivers/clk/mediatek/Kconfig
35 @@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS
36 This driver supports MediaTek MT7629 HIFSYS clocks providing
37 to PCI-E and USB.
38
39 +config COMMON_CLK_MT7981
40 + bool "Clock driver for MediaTek MT7981"
41 + depends on ARCH_MEDIATEK || COMPILE_TEST
42 + select COMMON_CLK_MEDIATEK
43 + default ARCH_MEDIATEK
44 + help
45 + This driver supports MediaTek MT7981 basic clocks and clocks
46 + required for various peripherals found on this SoC.
47 +
48 +config COMMON_CLK_MT7981_ETHSYS
49 + tristate "Clock driver for MediaTek MT7981 ETHSYS"
50 + depends on COMMON_CLK_MT7981
51 + default COMMON_CLK_MT7981
52 + help
53 + This driver adds support for clocks for Ethernet and SGMII
54 + required on MediaTek MT7981 SoC.
55 +
56 config COMMON_CLK_MT7986
57 bool "Clock driver for MediaTek MT7986"
58 depends on ARCH_MEDIATEK || COMPILE_TEST
59 --- a/drivers/clk/mediatek/Makefile
60 +++ b/drivers/clk/mediatek/Makefile
61 @@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
62 obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
63 obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
64 obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
65 +obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
66 +obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
67 +obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
68 +obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
69 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
70 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
71 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
72 --- /dev/null
73 +++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c
74 @@ -0,0 +1,102 @@
75 +// SPDX-License-Identifier: GPL-2.0
76 +/*
77 + * Copyright (c) 2021 MediaTek Inc.
78 + * Author: Sam Shih <sam.shih@mediatek.com>
79 + * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
80 + * Author: Jianhui Zhao <zhaojh329@gmail.com>
81 + * Author: Daniel Golle <daniel@makrotopia.org>
82 + */
83 +
84 +#include <linux/clk-provider.h>
85 +#include <linux/of.h>
86 +#include <linux/of_address.h>
87 +#include <linux/of_device.h>
88 +#include <linux/platform_device.h>
89 +
90 +#include "clk-gate.h"
91 +#include "clk-mtk.h"
92 +#include "clk-mux.h"
93 +#include "clk-pll.h"
94 +
95 +#include <dt-bindings/clock/mediatek,mt7981-clk.h>
96 +#include <linux/clk.h>
97 +
98 +#define MT7981_PLL_FMAX (2500UL * MHZ)
99 +#define CON0_MT7981_RST_BAR BIT(27)
100 +
101 +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
102 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
103 + _div_table, _parent_name) \
104 + { \
105 + .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
106 + .en_mask = _en_mask, .flags = _flags, \
107 + .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \
108 + .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
109 + .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
110 + .pcw_shift = _pcw_shift, .div_table = _div_table, \
111 + .parent_name = _parent_name, \
112 + }
113 +
114 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
115 + _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
116 + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
117 + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
118 + "clkxtal")
119 +
120 +static const struct mtk_pll_data plls[] = {
121 + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
122 + 32, 0x0200, 4, 0, 0x0204, 0),
123 + PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
124 + 0x0210, 4, 0, 0x0214, 0),
125 + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
126 + 0x0220, 4, 0, 0x0224, 0),
127 + PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
128 + 0x0230, 4, 0, 0x0234, 0),
129 + PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
130 + 0x0240, 4, 0, 0x0244, 0),
131 + PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
132 + 0x0250, 4, 0, 0x0254, 0),
133 + PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
134 + 0x0260, 4, 0, 0x0264, 0),
135 + PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
136 + 0x0278, 4, 0, 0x027C, 0),
137 +};
138 +
139 +static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
140 + { .compatible = "mediatek,mt7981-apmixedsys", },
141 + { /* sentinel */ }
142 +};
143 +
144 +static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
145 +{
146 + struct clk_hw_onecell_data *clk_data;
147 + struct device_node *node = pdev->dev.of_node;
148 + int r;
149 +
150 + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
151 + if (!clk_data)
152 + return -ENOMEM;
153 +
154 + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
155 +
156 + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
157 + if (r) {
158 + pr_err("%s(): could not register clock provider: %d\n",
159 + __func__, r);
160 + goto free_apmixed_data;
161 + }
162 + return r;
163 +
164 +free_apmixed_data:
165 + mtk_free_clk_data(clk_data);
166 + return r;
167 +}
168 +
169 +static struct platform_driver clk_mt7981_apmixed_drv = {
170 + .probe = clk_mt7981_apmixed_probe,
171 + .driver = {
172 + .name = "clk-mt7981-apmixed",
173 + .of_match_table = of_match_clk_mt7981_apmixed,
174 + },
175 +};
176 +builtin_platform_driver(clk_mt7981_apmixed_drv);
177 --- /dev/null
178 +++ b/drivers/clk/mediatek/clk-mt7981-eth.c
179 @@ -0,0 +1,118 @@
180 +// SPDX-License-Identifier: GPL-2.0
181 +/*
182 + * Copyright (c) 2021 MediaTek Inc.
183 + * Author: Sam Shih <sam.shih@mediatek.com>
184 + * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
185 + * Author: Jianhui Zhao <zhaojh329@gmail.com>
186 + * Author: Daniel Golle <daniel@makrotopia.org>
187 + */
188 +
189 +#include <linux/clk-provider.h>
190 +#include <linux/of.h>
191 +#include <linux/of_address.h>
192 +#include <linux/of_device.h>
193 +#include <linux/platform_device.h>
194 +
195 +#include "clk-mtk.h"
196 +#include "clk-gate.h"
197 +
198 +#include <dt-bindings/clock/mediatek,mt7981-clk.h>
199 +
200 +static const struct mtk_gate_regs sgmii0_cg_regs = {
201 + .set_ofs = 0xE4,
202 + .clr_ofs = 0xE4,
203 + .sta_ofs = 0xE4,
204 +};
205 +
206 +#define GATE_SGMII0(_id, _name, _parent, _shift) { \
207 + .id = _id, \
208 + .name = _name, \
209 + .parent_name = _parent, \
210 + .regs = &sgmii0_cg_regs, \
211 + .shift = _shift, \
212 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
213 + }
214 +
215 +static const struct mtk_gate sgmii0_clks[] __initconst = {
216 + GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
217 + GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
218 + GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
219 + GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
220 +};
221 +
222 +static const struct mtk_gate_regs sgmii1_cg_regs = {
223 + .set_ofs = 0xE4,
224 + .clr_ofs = 0xE4,
225 + .sta_ofs = 0xE4,
226 +};
227 +
228 +#define GATE_SGMII1(_id, _name, _parent, _shift) { \
229 + .id = _id, \
230 + .name = _name, \
231 + .parent_name = _parent, \
232 + .regs = &sgmii1_cg_regs, \
233 + .shift = _shift, \
234 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
235 + }
236 +
237 +static const struct mtk_gate sgmii1_clks[] __initconst = {
238 + GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
239 + GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
240 + GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
241 + GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
242 +};
243 +
244 +static const struct mtk_gate_regs eth_cg_regs = {
245 + .set_ofs = 0x30,
246 + .clr_ofs = 0x30,
247 + .sta_ofs = 0x30,
248 +};
249 +
250 +#define GATE_ETH(_id, _name, _parent, _shift) { \
251 + .id = _id, \
252 + .name = _name, \
253 + .parent_name = _parent, \
254 + .regs = &eth_cg_regs, \
255 + .shift = _shift, \
256 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
257 + }
258 +
259 +static const struct mtk_gate eth_clks[] __initconst = {
260 + GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
261 + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
262 + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
263 + GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
264 +};
265 +
266 +static const struct mtk_clk_desc eth_desc = {
267 + .clks = eth_clks,
268 + .num_clks = ARRAY_SIZE(eth_clks),
269 +};
270 +
271 +static const struct mtk_clk_desc sgmii0_desc = {
272 + .clks = sgmii0_clks,
273 + .num_clks = ARRAY_SIZE(sgmii0_clks),
274 +};
275 +
276 +static const struct mtk_clk_desc sgmii1_desc = {
277 + .clks = sgmii1_clks,
278 + .num_clks = ARRAY_SIZE(sgmii1_clks),
279 +};
280 +
281 +static const struct of_device_id of_match_clk_mt7981_eth[] = {
282 + { .compatible = "mediatek,mt7981-ethsys", .data = &eth_desc },
283 + { .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },
284 + { .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },
285 + { /* sentinel */ }
286 +};
287 +
288 +static struct platform_driver clk_mt7981_eth_drv = {
289 + .probe = mtk_clk_simple_probe,
290 + .remove = mtk_clk_simple_remove,
291 + .driver = {
292 + .name = "clk-mt7981-eth",
293 + .of_match_table = of_match_clk_mt7981_eth,
294 + },
295 +};
296 +module_platform_driver(clk_mt7981_eth_drv);
297 +MODULE_LICENSE("GPL v2");
298 --- /dev/null
299 +++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c
300 @@ -0,0 +1,207 @@
301 +// SPDX-License-Identifier: GPL-2.0
302 +/*
303 + * Copyright (c) 2021 MediaTek Inc.
304 + * Author: Sam Shih <sam.shih@mediatek.com>
305 + * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
306 + * Author: Jianhui Zhao <zhaojh329@gmail.com>
307 + * Author: Daniel Golle <daniel@makrotopia.org>
308 + */
309 +
310 +#include <linux/clk-provider.h>
311 +#include <linux/of.h>
312 +#include <linux/of_address.h>
313 +#include <linux/of_device.h>
314 +#include <linux/platform_device.h>
315 +#include "clk-mtk.h"
316 +#include "clk-gate.h"
317 +#include "clk-mux.h"
318 +
319 +#include <dt-bindings/clock/mediatek,mt7981-clk.h>
320 +#include <linux/clk.h>
321 +
322 +static DEFINE_SPINLOCK(mt7981_clk_lock);
323 +
324 +static const struct mtk_fixed_factor infra_divs[] = {
325 + FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
326 +};
327 +
328 +static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
329 + "uart_sel" };
330 +
331 +static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
332 + "spi_sel" };
333 +
334 +static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
335 + "spim_mst_sel" };
336 +
337 +static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
338 +
339 +static const char *const infra_pwm_bsel_parents[] __initconst = {
340 + "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
341 +};
342 +
343 +static const char *const infra_pcie_parents[] __initconst = {
344 + "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
345 +};
346 +
347 +static const struct mtk_mux infra_muxes[] = {
348 + /* MODULE_CLK_SEL_0 */
349 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
350 + infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
351 + -1, -1, -1),
352 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
353 + infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
354 + -1, -1, -1),
355 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
356 + infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
357 + -1, -1, -1),
358 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
359 + infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
360 + -1, -1, -1),
361 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
362 + infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
363 + -1, -1, -1),
364 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
365 + infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
366 + -1, -1, -1),
367 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
368 + infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
369 + -1, -1, -1),
370 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
371 + infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
372 + -1, -1, -1),
373 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
374 + infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
375 + -1, -1, -1),
376 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
377 + infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
378 + 2, -1, -1, -1),
379 + /* MODULE_CLK_SEL_1 */
380 + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
381 + infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
382 + -1, -1, -1),
383 +};
384 +
385 +static const struct mtk_gate_regs infra0_cg_regs = {
386 + .set_ofs = 0x40,
387 + .clr_ofs = 0x44,
388 + .sta_ofs = 0x48,
389 +};
390 +
391 +static const struct mtk_gate_regs infra1_cg_regs = {
392 + .set_ofs = 0x50,
393 + .clr_ofs = 0x54,
394 + .sta_ofs = 0x58,
395 +};
396 +
397 +static const struct mtk_gate_regs infra2_cg_regs = {
398 + .set_ofs = 0x60,
399 + .clr_ofs = 0x64,
400 + .sta_ofs = 0x68,
401 +};
402 +
403 +#define GATE_INFRA0(_id, _name, _parent, _shift) \
404 + { \
405 + .id = _id, .name = _name, .parent_name = _parent, \
406 + .regs = &infra0_cg_regs, .shift = _shift, \
407 + .ops = &mtk_clk_gate_ops_setclr, \
408 + }
409 +
410 +#define GATE_INFRA1(_id, _name, _parent, _shift) \
411 + { \
412 + .id = _id, .name = _name, .parent_name = _parent, \
413 + .regs = &infra1_cg_regs, .shift = _shift, \
414 + .ops = &mtk_clk_gate_ops_setclr, \
415 + }
416 +
417 +#define GATE_INFRA2(_id, _name, _parent, _shift) \
418 + { \
419 + .id = _id, .name = _name, .parent_name = _parent, \
420 + .regs = &infra2_cg_regs, .shift = _shift, \
421 + .ops = &mtk_clk_gate_ops_setclr, \
422 + }
423 +
424 +static const struct mtk_gate infra_clks[] = {
425 + /* INFRA0 */
426 + GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
427 + GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
428 + GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
429 + GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
430 + GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
431 + GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
432 +
433 + GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
434 + GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
435 + GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
436 + GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
437 + GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
438 + GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
439 + 14),
440 + GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
441 + GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
442 + GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
443 + GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
444 + GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
445 + /* INFRA1 */
446 + GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
447 + GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
448 + GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
449 + GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
450 + GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
451 + GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
452 + GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
453 + GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
454 + GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
455 + GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
456 + GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
457 + GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
458 + GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
459 + 13),
460 + GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
461 + 14),
462 + GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
463 + GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
464 + GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
465 + GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
466 + GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
467 + GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
468 + GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
469 + GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
470 + GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
471 + GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
472 + /* INFRA2 */
473 + GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
474 + GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
475 + GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
476 + GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
477 + GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
478 + GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
479 + 13),
480 + GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
481 + GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
482 +};
483 +
484 +static const struct mtk_clk_desc infracfg_desc = {
485 + .factor_clks = infra_divs,
486 + .num_factor_clks = ARRAY_SIZE(infra_divs),
487 + .mux_clks = infra_muxes,
488 + .num_mux_clks = ARRAY_SIZE(infra_muxes),
489 + .clks = infra_clks,
490 + .num_clks = ARRAY_SIZE(infra_clks),
491 + .clk_lock = &mt7981_clk_lock,
492 +};
493 +
494 +static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
495 + { .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc },
496 + { /* sentinel */ }
497 +};
498 +
499 +static struct platform_driver clk_mt7981_infracfg_drv = {
500 + .probe = mtk_clk_simple_probe,
501 + .remove = mtk_clk_simple_remove,
502 + .driver = {
503 + .name = "clk-mt7981-infracfg",
504 + .of_match_table = of_match_clk_mt7981_infracfg,
505 + },
506 +};
507 +builtin_platform_driver(clk_mt7981_infracfg_drv);
508 --- /dev/null
509 +++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
510 @@ -0,0 +1,422 @@
511 +// SPDX-License-Identifier: GPL-2.0
512 +/*
513 + * Copyright (c) 2021 MediaTek Inc.
514 + * Author: Sam Shih <sam.shih@mediatek.com>
515 + * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
516 + * Author: Jianhui Zhao <zhaojh329@gmail.com>
517 + */
518 +
519 +
520 +#include <linux/clk-provider.h>
521 +#include <linux/of.h>
522 +#include <linux/of_address.h>
523 +#include <linux/of_device.h>
524 +#include <linux/platform_device.h>
525 +#include "clk-mtk.h"
526 +#include "clk-gate.h"
527 +#include "clk-mux.h"
528 +
529 +#include <dt-bindings/clock/mediatek,mt7981-clk.h>
530 +#include <linux/clk.h>
531 +
532 +static DEFINE_SPINLOCK(mt7981_clk_lock);
533 +
534 +static const struct mtk_fixed_factor top_divs[] = {
535 + FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
536 + FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
537 + FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
538 + FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
539 + FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
540 + FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
541 + FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
542 + FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
543 + FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
544 + FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
545 + FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
546 + FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
547 + FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
548 + FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
549 + FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
550 + FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
551 + FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
552 + FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
553 + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
554 + FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
555 + FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
556 + FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
557 + FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
558 + FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
559 + FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
560 + FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
561 + FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
562 + FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
563 + FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
564 + FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
565 + FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
566 + FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
567 + FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
568 + FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
569 + FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
570 + FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
571 + FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
572 + FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
573 + FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
574 + FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
575 + FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
576 + FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
577 + FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
578 + FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
579 + FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
580 + FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
581 + FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
582 + FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
583 + FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
584 + FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
585 + FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
586 + FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
587 + FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
588 + FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
589 + FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
590 + FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
591 + FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
592 + FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
593 + FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
594 + FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
595 + FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
596 + FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
597 + FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
598 + FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
599 + FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
600 + FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
601 + FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
602 + FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
603 + FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
604 + FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
605 + FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
606 + FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
607 + FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
608 + FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
609 + FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
610 + FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
611 +};
612 +
613 +static const char * const nfi1x_parents[] __initconst = {
614 + "cb_cksq_40m",
615 + "cb_mm_d4",
616 + "net1_d8_d2",
617 + "cb_net2_d6",
618 + "cb_m_d4",
619 + "cb_mm_d8",
620 + "net1_d8_d4",
621 + "cb_m_d8"
622 +};
623 +
624 +static const char * const spinfi_parents[] __initconst = {
625 + "cksq_40m_d2",
626 + "cb_cksq_40m",
627 + "net1_d5_d4",
628 + "cb_m_d4",
629 + "cb_mm_d8",
630 + "net1_d8_d4",
631 + "mm_d6_d2",
632 + "cb_m_d8"
633 +};
634 +
635 +static const char * const spi_parents[] __initconst = {
636 + "cb_cksq_40m",
637 + "cb_m_d2",
638 + "cb_mm_d4",
639 + "net1_d8_d2",
640 + "cb_net2_d6",
641 + "net1_d5_d4",
642 + "cb_m_d4",
643 + "net1_d8_d4"
644 +};
645 +
646 +static const char * const uart_parents[] __initconst = {
647 + "cb_cksq_40m",
648 + "cb_m_d8",
649 + "m_d8_d2"
650 +};
651 +
652 +static const char * const pwm_parents[] __initconst = {
653 + "cb_cksq_40m",
654 + "net1_d8_d2",
655 + "net1_d5_d4",
656 + "cb_m_d4",
657 + "m_d8_d2",
658 + "cb_rtc_32k"
659 +};
660 +
661 +static const char * const i2c_parents[] __initconst = {
662 + "cb_cksq_40m",
663 + "net1_d5_d4",
664 + "cb_m_d4",
665 + "net1_d8_d4"
666 +};
667 +
668 +static const char * const pextp_tl_ck_parents[] __initconst = {
669 + "cb_cksq_40m",
670 + "net1_d5_d4",
671 + "cb_m_d4",
672 + "cb_rtc_32k"
673 +};
674 +
675 +static const char * const emmc_208m_parents[] __initconst = {
676 + "cb_cksq_40m",
677 + "cb_m_d2",
678 + "cb_net2_d4",
679 + "cb_apll2_196m",
680 + "cb_mm_d4",
681 + "net1_d8_d2",
682 + "cb_mm_d6"
683 +};
684 +
685 +static const char * const emmc_400m_parents[] __initconst = {
686 + "cb_cksq_40m",
687 + "cb_net2_d2",
688 + "cb_mm_d2",
689 + "cb_net2_d2"
690 +};
691 +
692 +static const char * const csw_f26m_parents[] __initconst = {
693 + "cksq_40m_d2",
694 + "m_d8_d2"
695 +};
696 +
697 +static const char * const dramc_md32_parents[] __initconst = {
698 + "cb_cksq_40m",
699 + "cb_m_d2",
700 + "cb_wedmcu_208m"
701 +};
702 +
703 +static const char * const sysaxi_parents[] __initconst = {
704 + "cb_cksq_40m",
705 + "net1_d8_d2"
706 +};
707 +
708 +static const char * const sysapb_parents[] __initconst = {
709 + "cb_cksq_40m",
710 + "m_d3_d2"
711 +};
712 +
713 +static const char * const arm_db_main_parents[] __initconst = {
714 + "cb_cksq_40m",
715 + "cb_net2_d6"
716 +};
717 +
718 +static const char * const ap2cnn_host_parents[] __initconst = {
719 + "cb_cksq_40m",
720 + "net1_d8_d4"
721 +};
722 +
723 +static const char * const netsys_parents[] __initconst = {
724 + "cb_cksq_40m",
725 + "cb_mm_d2"
726 +};
727 +
728 +static const char * const netsys_500m_parents[] __initconst = {
729 + "cb_cksq_40m",
730 + "cb_net1_d5"
731 +};
732 +
733 +static const char * const netsys_mcu_parents[] __initconst = {
734 + "cb_cksq_40m",
735 + "cb_mm_720m",
736 + "cb_net1_d4",
737 + "cb_net1_d5",
738 + "cb_m_416m"
739 +};
740 +
741 +static const char * const netsys_2x_parents[] __initconst = {
742 + "cb_cksq_40m",
743 + "cb_net2_800m",
744 + "cb_mm_720m"
745 +};
746 +
747 +static const char * const sgm_325m_parents[] __initconst = {
748 + "cb_cksq_40m",
749 + "cb_sgm_325m"
750 +};
751 +
752 +static const char * const sgm_reg_parents[] __initconst = {
753 + "cb_cksq_40m",
754 + "cb_net2_d4"
755 +};
756 +
757 +static const char * const eip97b_parents[] __initconst = {
758 + "cb_cksq_40m",
759 + "cb_net1_d5",
760 + "cb_m_416m",
761 + "cb_mm_d2",
762 + "net1_d5_d2"
763 +};
764 +
765 +static const char * const aud_parents[] __initconst = {
766 + "cb_cksq_40m",
767 + "cb_apll2_196m"
768 +};
769 +
770 +static const char * const a1sys_parents[] __initconst = {
771 + "cb_cksq_40m",
772 + "apll2_d4"
773 +};
774 +
775 +static const char * const aud_l_parents[] __initconst = {
776 + "cb_cksq_40m",
777 + "cb_apll2_196m",
778 + "m_d8_d2"
779 +};
780 +
781 +static const char * const a_tuner_parents[] __initconst = {
782 + "cb_cksq_40m",
783 + "apll2_d4",
784 + "m_d8_d2"
785 +};
786 +
787 +static const char * const u2u3_parents[] __initconst = {
788 + "cb_cksq_40m",
789 + "m_d8_d2"
790 +};
791 +
792 +static const char * const u2u3_sys_parents[] __initconst = {
793 + "cb_cksq_40m",
794 + "net1_d5_d4"
795 +};
796 +
797 +static const char * const usb_frmcnt_parents[] __initconst = {
798 + "cb_cksq_40m",
799 + "cb_mm_d3_d5"
800 +};
801 +
802 +static const struct mtk_mux top_muxes[] = {
803 + /* CLK_CFG_0 */
804 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
805 + 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
806 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
807 + 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
808 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
809 + 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
810 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
811 + 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
812 + /* CLK_CFG_1 */
813 + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
814 + 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
815 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
816 + 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
817 + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
818 + 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
819 + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
820 + pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
821 + 0x1C0, 7),
822 + /* CLK_CFG_2 */
823 + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
824 + emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
825 + 0x1C0, 8),
826 + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
827 + emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
828 + 0x1C0, 9),
829 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
830 + csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
831 + 0x1C0, 10,
832 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
833 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
834 + csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
835 + 31, 0x1C0, 11,
836 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
837 + /* CLK_CFG_3 */
838 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
839 + dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
840 + 7, 0x1C0, 12,
841 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
842 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
843 + sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
844 + 0x1C0, 13,
845 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
846 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
847 + sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
848 + 23, 0x1C0, 14,
849 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
850 + MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
851 + arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
852 + 0x1C0, 15),
853 + /* CLK_CFG_4 */
854 + MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
855 + ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
856 + 0x1C0, 16),
857 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
858 + 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
859 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
860 + netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
861 + 0x1C0, 18),
862 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
863 + netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
864 + 0x1C0, 19),
865 + /* CLK_CFG_5 */
866 + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
867 + netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
868 + 0x1C0, 20),
869 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
870 + sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
871 + 0x1C0, 21),
872 + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
873 + 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
874 + MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
875 + 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
876 + /* CLK_CFG_6 */
877 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
878 + csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
879 + 7, 0x1C0, 24),
880 + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
881 + 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
882 + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
883 + 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
884 + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
885 + 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
886 + /* CLK_CFG_7 */
887 + MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
888 + a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
889 + 0x1C0, 28),
890 + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
891 + 0x074, 0x078, 8, 1, 15, 0x1C0, 29),
892 + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
893 + u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
894 + 0x1C0, 30),
895 + MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
896 + u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
897 + 0x1C4, 0),
898 + /* CLK_CFG_8 */
899 + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
900 + usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
901 + 0x1C4, 1),
902 +};
903 +
904 +static struct mtk_composite top_aud_divs[] = {
905 + DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
906 + 0x0420, 0, 0x0420, 8, 8),
907 +};
908 +
909 +static const struct mtk_clk_desc topck_desc = {
910 + .factor_clks = top_divs,
911 + .num_factor_clks = ARRAY_SIZE(top_divs),
912 + .mux_clks = top_muxes,
913 + .num_mux_clks = ARRAY_SIZE(top_muxes),
914 + .composite_clks = top_aud_divs,
915 + .num_composite_clks = ARRAY_SIZE(top_aud_divs),
916 + .clk_lock = &mt7981_clk_lock,
917 +};
918 +
919 +static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
920 + { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc },
921 + { /* sentinel */ }
922 +};
923 +
924 +static struct platform_driver clk_mt7981_topckgen_drv = {
925 + .probe = mtk_clk_simple_probe,
926 + .remove = mtk_clk_simple_remove,
927 + .driver = {
928 + .name = "clk-mt7981-topckgen",
929 + .of_match_table = of_match_clk_mt7981_topckgen,
930 + },
931 +};
932 +builtin_platform_driver(clk_mt7981_topckgen_drv);
Staging tree of Stijn Tintel