target/linux/mediatek/patches-6.6/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch

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  40 Date: Tue, 26 Apr 2022 20:51:36 +0100
  41 From: Daniel Golle <daniel@makrotopia.org>
  42 To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,
  43  linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
  44 Cc: Rob Herring <robh+dt@kernel.org>,
  45  Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
  46  Matthias Brugger <matthias.bgg@gmail.com>
  47 Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
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  70
  71 With the current range specified for the CPU interface there is an
  72 error message at boot:
  73
  74 GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
  75
  76 Setting irqchip.gicv2_force_probe=1 in bootargs results in:
  77
  78 GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
  79 GIC: Adjusting CPU interface base to 0x000000001032f000
  80 GIC: Using split EOI/Deactivate mode
  81
  82 Using the adjusted CPU interface base and 8K size results in only the
  83 final line remaining and fully working system as well as /proc/interrupts
  84 showing additional IPI3,4,5,6:
  85
  86 IPI3:         0          0       CPU stop (for crash dump) interrupts
  87 IPI4:         0          0       Timer broadcast interrupts
  88 IPI5:         0          0       IRQ work interrupts
  89 IPI6:         0          0       CPU wake-up interrupts
  90
  91 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  92 ---
  93  arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
  94  1 file changed, 1 insertion(+), 1 deletion(-)
  95
  96 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  97 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  98 @@ -346,7 +346,7 @@
  99                 #interrupt-cells = <3>;
 100                 interrupt-parent = <&gic>;
 101                 reg = <0 0x10310000 0 0x1000>,
 102 -                     <0 0x10320000 0 0x1000>,
 103 +                     <0 0x1032f000 0 0x2000>,
 104                       <0 0x10340000 0 0x2000>,
 105                       <0 0x10360000 0 0x2000>;
 106         };