target/linux/mediatek/patches-6.6/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch

   1 From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001
   2 From: Sam Shih <sam.shih@mediatek.com>
   3 Date: Fri, 6 Jan 2023 16:28:44 +0100
   4 Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes
   5
   6 This patch adds PCIe support for MT7986.
   7
   8 Signed-off-by: Jieyy Yang <jieyy.yang@mediatek.com>
   9 Signed-off-by: Sam Shih <sam.shih@mediatek.com>
  10 Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
  11 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  12 Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de
  13 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  14 ---
  15  arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++
  16  arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 52 ++++++++++++++++++++
  17  2 files changed, 68 insertions(+)
  18
  19 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
  20 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
  21 @@ -93,6 +93,15 @@
  22         non-removable;
  23         no-sd;
  24         no-sdio;
  25 +};
  26 +
  27 +&pcie {
  28 +       pinctrl-names = "default";
  29 +       pinctrl-0 = <&pcie_pins>;
  30 +       status = "okay";
  31 +};
  32 +
  33 +&pcie_phy {
  34         status = "okay";
  35  };
  36
  37 @@ -155,6 +164,13 @@
  38                 };
  39         };
  40
  41 +       pcie_pins: pcie-pins {
  42 +               mux {
  43 +                       function = "pcie";
  44 +                       groups = "pcie_clk", "pcie_wake", "pcie_pereset";
  45 +               };
  46 +       };
  47 +
  48         spi_flash_pins: spi-flash-pins {
  49                 mux {
  50                         function = "spi";
  51 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
  52 +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
  53 @@ -8,6 +8,7 @@
  54  #include <dt-bindings/interrupt-controller/arm-gic.h>
  55  #include <dt-bindings/clock/mt7986-clk.h>
  56  #include <dt-bindings/reset/mt7986-resets.h>
  57 +#include <dt-bindings/phy/phy.h>
  58
  59  / {
  60         compatible = "mediatek,mt7986a";
  61 @@ -360,6 +361,57 @@
  62                         status = "disabled";
  63                 };
  64
  65 +               pcie: pcie@11280000 {
  66 +                       compatible = "mediatek,mt7986-pcie",
  67 +                                    "mediatek,mt8192-pcie";
  68 +                       device_type = "pci";
  69 +                       #address-cells = <3>;
  70 +                       #size-cells = <2>;
  71 +                       reg = <0x00 0x11280000 0x00 0x4000>;
  72 +                       reg-names = "pcie-mac";
  73 +                       interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
  74 +                       bus-range = <0x00 0xff>;
  75 +                       ranges = <0x82000000 0x00 0x20000000 0x00
  76 +                                 0x20000000 0x00 0x10000000>;
  77 +                       clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
  78 +                                <&infracfg CLK_INFRA_IPCIE_CK>,
  79 +                                <&infracfg CLK_INFRA_IPCIER_CK>,
  80 +                                <&infracfg CLK_INFRA_IPCIEB_CK>;
  81 +                       clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
  82 +                       status = "disabled";
  83 +
  84 +                       phys = <&pcie_port PHY_TYPE_PCIE>;
  85 +                       phy-names = "pcie-phy";
  86 +
  87 +                       #interrupt-cells = <1>;
  88 +                       interrupt-map-mask = <0 0 0 0x7>;
  89 +                       interrupt-map = <0 0 0 1 &pcie_intc 0>,
  90 +                                       <0 0 0 2 &pcie_intc 1>,
  91 +                                       <0 0 0 3 &pcie_intc 2>,
  92 +                                       <0 0 0 4 &pcie_intc 3>;
  93 +                       pcie_intc: interrupt-controller {
  94 +                               #address-cells = <0>;
  95 +                               #interrupt-cells = <1>;
  96 +                               interrupt-controller;
  97 +                       };
  98 +               };
  99 +
 100 +               pcie_phy: t-phy@11c00000 {
 101 +                       compatible = "mediatek,mt7986-tphy",
 102 +                                    "mediatek,generic-tphy-v2";
 103 +                       #address-cells = <2>;
 104 +                       #size-cells = <2>;
 105 +                       ranges;
 106 +                       status = "disabled";
 107 +
 108 +                       pcie_port: pcie-phy@11c00000 {
 109 +                               reg = <0 0x11c00000 0 0x20000>;
 110 +                               clocks = <&clk40m>;
 111 +                               clock-names = "ref";
 112 +                               #phy-cells = <1>;
 113 +                       };
 114 +               };
 115 +
 116                 usb_phy: t-phy@11e10000 {
 117                         compatible = "mediatek,mt7986-tphy",
 118                                      "mediatek,generic-tphy-v2";