target/linux/mediatek/patches-6.6/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch

   1 From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001
   2 From: Sam Shih <sam.shih@mediatek.com>
   3 Date: Fri, 18 Nov 2022 20:01:21 +0100
   4 Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes
   5
   6 This patch adds spi support for MT7986.
   7
   8 Signed-off-by: Sam Shih <sam.shih@mediatek.com>
   9 Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
  10 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  11 Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
  12 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  13 ---
  14  arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++
  15  arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 28 ++++++++++++++++
  16  arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++
  17  3 files changed, 98 insertions(+)
  18
  19 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
  20 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
  21 @@ -59,6 +59,20 @@
  22  };
  23
  24  &pio {
  25 +       spi_flash_pins: spi-flash-pins {
  26 +               mux {
  27 +                       function = "spi";
  28 +                       groups = "spi0", "spi0_wp_hold";
  29 +               };
  30 +       };
  31 +
  32 +       spic_pins: spic-pins {
  33 +               mux {
  34 +                       function = "spi";
  35 +                       groups = "spi1_2";
  36 +               };
  37 +       };
  38 +
  39         uart1_pins: uart1-pins {
  40                 mux {
  41                         function = "uart";
  42 @@ -105,6 +119,27 @@
  43         };
  44  };
  45
  46 +&spi0 {
  47 +       pinctrl-names = "default";
  48 +       pinctrl-0 = <&spi_flash_pins>;
  49 +       cs-gpios = <0>, <0>;
  50 +       status = "okay";
  51 +       spi_nand: spi_nand@0 {
  52 +               compatible = "spi-nand";
  53 +               reg = <0>;
  54 +               spi-max-frequency = <10000000>;
  55 +               spi-tx-bus-width = <4>;
  56 +               spi-rx-bus-width = <4>;
  57 +       };
  58 +};
  59 +
  60 +&spi1 {
  61 +       pinctrl-names = "default";
  62 +       pinctrl-0 = <&spic_pins>;
  63 +       cs-gpios = <0>, <0>;
  64 +       status = "okay";
  65 +};
  66 +
  67  &switch {
  68         ports {
  69                 #address-cells = <1>;
  70 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
  71 +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
  72 @@ -294,6 +294,34 @@
  73                         status = "disabled";
  74                 };
  75
  76 +               spi0: spi@1100a000 {
  77 +                       compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
  78 +                       #address-cells = <1>;
  79 +                       #size-cells = <0>;
  80 +                       reg = <0 0x1100a000 0 0x100>;
  81 +                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
  82 +                       clocks = <&topckgen CLK_TOP_MPLL_D2>,
  83 +                                <&topckgen CLK_TOP_SPI_SEL>,
  84 +                                <&infracfg CLK_INFRA_SPI0_CK>,
  85 +                                <&infracfg CLK_INFRA_SPI0_HCK_CK>;
  86 +                       clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
  87 +                       status = "disabled";
  88 +               };
  89 +
  90 +               spi1: spi@1100b000 {
  91 +                       compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
  92 +                       #address-cells = <1>;
  93 +                       #size-cells = <0>;
  94 +                       reg = <0 0x1100b000 0 0x100>;
  95 +                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
  96 +                       clocks = <&topckgen CLK_TOP_MPLL_D2>,
  97 +                                <&topckgen CLK_TOP_SPIM_MST_SEL>,
  98 +                                <&infracfg CLK_INFRA_SPI1_CK>,
  99 +                                <&infracfg CLK_INFRA_SPI1_HCK_CK>;
 100 +                       clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 101 +                       status = "disabled";
 102 +               };
 103 +
 104                 ethsys: syscon@15000000 {
 105                          #address-cells = <1>;
 106                          #size-cells = <1>;
 107 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
 108 +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
 109 @@ -100,6 +100,20 @@
 110  };
 111
 112  &pio {
 113 +       spi_flash_pins: spi-flash-pins {
 114 +               mux {
 115 +                       function = "spi";
 116 +                       groups = "spi0", "spi0_wp_hold";
 117 +               };
 118 +       };
 119 +
 120 +       spic_pins: spic-pins {
 121 +               mux {
 122 +                       function = "spi";
 123 +                       groups = "spi1_2";
 124 +               };
 125 +       };
 126 +
 127         wf_2g_5g_pins: wf-2g-5g-pins {
 128                 mux {
 129                         function = "wifi";
 130 @@ -132,6 +146,27 @@
 131         };
 132  };
 133
 134 +&spi0 {
 135 +       pinctrl-names = "default";
 136 +       pinctrl-0 = <&spi_flash_pins>;
 137 +       cs-gpios = <0>, <0>;
 138 +       status = "okay";
 139 +       spi_nand: spi_nand@0 {
 140 +               compatible = "spi-nand";
 141 +               reg = <0>;
 142 +               spi-max-frequency = <10000000>;
 143 +               spi-tx-bus-width = <4>;
 144 +               spi-rx-bus-width = <4>;
 145 +       };
 146 +};
 147 +
 148 +&spi1 {
 149 +       pinctrl-names = "default";
 150 +       pinctrl-0 = <&spic_pins>;
 151 +       cs-gpios = <0>, <0>;
 152 +       status = "okay";
 153 +};
 154 +
 155  &uart0 {
 156         status = "okay";
 157  };