target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch

   1 From: qizhong cheng <qizhong.cheng@mediatek.com>
   2 Date: Mon, 27 Dec 2021 21:31:10 +0800
   3 Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
   4  stabilize
   5 MIME-Version: 1.0
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   8
   9 Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
  10 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
  11 be delayed 100ms (TPVPERL) for the power and clock to become stable.
  12
  13 Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
  14 Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
  15 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  16 Acked-by: Pali Rohár <pali@kernel.org>
  17 ---
  18
  19 --- a/drivers/pci/controller/pcie-mediatek.c
  20 +++ b/drivers/pci/controller/pcie-mediatek.c
  21 @@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru
  22          */
  23         msleep(100);
  24
  25 +       /*
  26 +        * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
  27 +        * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
  28 +        * be delayed 100ms (TPVPERL) for the power and clock to become stable.
  29 +        */
  30 +       msleep(100);
  31 +
  32         /* De-assert PHY, PE, PIPE, MAC and configuration reset */
  33         val = readl(port->base + PCIE_RST_CTRL);
  34         val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |