target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch

   1 From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001
   2 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
   3 Date: Fri, 20 Jan 2023 10:20:33 +0100
   4 Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with
   5  mtk_clk_register_gates()
   6
   7 Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
   8 introduces a helper function for the sole purpose of propagating a
   9 struct device pointer to the clk API when registering the mtk-gate
  10 clocks to take advantage of Runtime PM when/where needed and where
  11 a power domain is defined in devicetree.
  12
  13 Function mtk_clk_register_gates() then becomes a wrapper around the
  14 new mtk_clk_register_gates_with_dev() function that will simply pass
  15 NULL as struct device: this is essential when registering drivers
  16 with CLK_OF_DECLARE instead of as a platform device, as there will
  17 be no struct device to pass... but we can as well simply have only
  18 one function that always takes such pointer as a param and pass NULL
  19 when unavoidable.
  20
  21 This commit removes the mtk_clk_register_gates() wrapper and renames
  22 mtk_clk_register_gates_with_dev() to the former and all of the calls
  23 to either of the two functions were fixed in all drivers in order to
  24 reflect this change; also, to improve consistency with other kernel
  25 functions, the pointer to struct device was moved as the first param.
  26
  27 Since a lot of MediaTek clock drivers are actually registering as a
  28 platform device, but were still registering the mtk-gate clocks
  29 without passing any struct device to the clock framework, they've
  30 been changed to pass a valid one now, as to make all those platforms
  31 able to use runtime power management where available.
  32
  33 While at it, some much needed indentation changes were also done.
  34
  35 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  36 Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
  37 Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
  38 Tested-by: Miles Chen <miles.chen@mediatek.com>
  39 Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com
  40 Tested-by: Mingming Su <mingming.su@mediatek.com>
  41 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  42
  43 [daniel@makrotopia.org: dropped parts not relevant for OpenWrt]
  44 ---
  45  drivers/clk/mediatek/clk-gate.c            | 23 +++++++---------------
  46  drivers/clk/mediatek/clk-gate.h            |  7 +------
  47  drivers/clk/mediatek/clk-mt2701-aud.c      |  4 ++--
  48  drivers/clk/mediatek/clk-mt2701-eth.c      |  4 ++--
  49  drivers/clk/mediatek/clk-mt2701-g3d.c      |  2 +-
  50  drivers/clk/mediatek/clk-mt2701-hif.c      |  4 ++--
  51  drivers/clk/mediatek/clk-mt2701-mm.c       |  4 ++--
  52  drivers/clk/mediatek/clk-mt2701.c          | 12 +++++------
  53  drivers/clk/mediatek/clk-mt2712-mm.c       |  4 ++--
  54  drivers/clk/mediatek/clk-mt2712.c          | 12 +++++------
  55  drivers/clk/mediatek/clk-mt7622-aud.c      |  4 ++--
  56  drivers/clk/mediatek/clk-mt7622-eth.c      |  8 ++++----
  57  drivers/clk/mediatek/clk-mt7622-hif.c      |  8 ++++----
  58  drivers/clk/mediatek/clk-mt7622.c          | 14 ++++++-------
  59  drivers/clk/mediatek/clk-mt7629-eth.c      |  7 ++++---
  60  drivers/clk/mediatek/clk-mt7629-hif.c      |  8 ++++----
  61  drivers/clk/mediatek/clk-mt7629.c          | 10 +++++-----
  62  drivers/clk/mediatek/clk-mt7986-eth.c      | 10 +++++-----
  63  drivers/clk/mediatek/clk-mt7986-infracfg.c |  4 ++--
  64  19 files changed, 68 insertions(+), 81 deletions(-)
  65
  66 --- a/drivers/clk/mediatek/clk-gate.c
  67 +++ b/drivers/clk/mediatek/clk-gate.c
  68 @@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no
  69  };
  70  EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
  71
  72 -static struct clk_hw *mtk_clk_register_gate(const char *name,
  73 +static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
  74                                          const char *parent_name,
  75                                          struct regmap *regmap, int set_ofs,
  76                                          int clr_ofs, int sta_ofs, u8 bit,
  77                                          const struct clk_ops *ops,
  78 -                                        unsigned long flags, struct device *dev)
  79 +                                        unsigned long flags)
  80  {
  81         struct mtk_clk_gate *cg;
  82         int ret;
  83 @@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru
  84         kfree(cg);
  85  }
  86
  87 -int mtk_clk_register_gates_with_dev(struct device_node *node,
  88 -                                   const struct mtk_gate *clks, int num,
  89 -                                   struct clk_hw_onecell_data *clk_data,
  90 -                                   struct device *dev)
  91 +int mtk_clk_register_gates(struct device *dev, struct device_node *node,
  92 +                          const struct mtk_gate *clks, int num,
  93 +                          struct clk_hw_onecell_data *clk_data)
  94  {
  95         int i;
  96         struct clk_hw *hw;
  97 @@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru
  98                         continue;
  99                 }
 100
 101 -               hw = mtk_clk_register_gate(gate->name, gate->parent_name,
 102 +               hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
 103                                             regmap,
 104                                             gate->regs->set_ofs,
 105                                             gate->regs->clr_ofs,
 106                                             gate->regs->sta_ofs,
 107                                             gate->shift, gate->ops,
 108 -                                           gate->flags, dev);
 109 +                                           gate->flags);
 110
 111                 if (IS_ERR(hw)) {
 112                         pr_err("Failed to register clk %s: %pe\n", gate->name,
 113 @@ -261,14 +260,6 @@ err:
 114
 115         return PTR_ERR(hw);
 116  }
 117 -EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev);
 118 -
 119 -int mtk_clk_register_gates(struct device_node *node,
 120 -                          const struct mtk_gate *clks, int num,
 121 -                          struct clk_hw_onecell_data *clk_data)
 122 -{
 123 -       return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
 124 -}
 125  EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
 126
 127  void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
 128 --- a/drivers/clk/mediatek/clk-gate.h
 129 +++ b/drivers/clk/mediatek/clk-gate.h
 130 @@ -50,15 +50,10 @@ struct mtk_gate {
 131  #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops)             \
 132         GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
 133
 134 -int mtk_clk_register_gates(struct device_node *node,
 135 +int mtk_clk_register_gates(struct device *dev, struct device_node *node,
 136                            const struct mtk_gate *clks, int num,
 137                            struct clk_hw_onecell_data *clk_data);
 138
 139 -int mtk_clk_register_gates_with_dev(struct device_node *node,
 140 -                                   const struct mtk_gate *clks, int num,
 141 -                                   struct clk_hw_onecell_data *clk_data,
 142 -                                   struct device *dev);
 143 -
 144  void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
 145                               struct clk_hw_onecell_data *clk_data);
 146
 147 --- a/drivers/clk/mediatek/clk-mt2701-aud.c
 148 +++ b/drivers/clk/mediatek/clk-mt2701-aud.c
 149 @@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p
 150
 151         clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
 152
 153 -       mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
 154 -                              clk_data);
 155 +       mtk_clk_register_gates(&pdev->dev, node, audio_clks,
 156 +                              ARRAY_SIZE(audio_clks), clk_data);
 157
 158         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 159         if (r) {
 160 --- a/drivers/clk/mediatek/clk-mt2701-eth.c
 161 +++ b/drivers/clk/mediatek/clk-mt2701-eth.c
 162 @@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p
 163
 164         clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
 165
 166 -       mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
 167 -                                               clk_data);
 168 +       mtk_clk_register_gates(&pdev->dev, node, eth_clks,
 169 +                              ARRAY_SIZE(eth_clks), clk_data);
 170
 171         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 172         if (r)
 173 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c
 174 +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
 175 @@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct
 176
 177         clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
 178
 179 -       mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
 180 +       mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
 181                                clk_data);
 182
 183         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 184 --- a/drivers/clk/mediatek/clk-mt2701-hif.c
 185 +++ b/drivers/clk/mediatek/clk-mt2701-hif.c
 186 @@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p
 187
 188         clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
 189
 190 -       mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
 191 -                                               clk_data);
 192 +       mtk_clk_register_gates(&pdev->dev, node, hif_clks,
 193 +                              ARRAY_SIZE(hif_clks), clk_data);
 194
 195         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 196         if (r) {
 197 --- a/drivers/clk/mediatek/clk-mt2701-mm.c
 198 +++ b/drivers/clk/mediatek/clk-mt2701-mm.c
 199 @@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl
 200
 201         clk_data = mtk_alloc_clk_data(CLK_MM_NR);
 202
 203 -       mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
 204 -                                               clk_data);
 205 +       mtk_clk_register_gates(&pdev->dev, node, mm_clks,
 206 +                              ARRAY_SIZE(mm_clks), clk_data);
 207
 208         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 209         if (r)
 210 --- a/drivers/clk/mediatek/clk-mt2701.c
 211 +++ b/drivers/clk/mediatek/clk-mt2701.c
 212 @@ -685,8 +685,8 @@ static int mtk_topckgen_init(struct plat
 213         mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
 214                                 base, &mt2701_clk_lock, clk_data);
 215
 216 -       mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
 217 -                                               clk_data);
 218 +       mtk_clk_register_gates(&pdev->dev, node, top_clks,
 219 +                              ARRAY_SIZE(top_clks), clk_data);
 220
 221         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 222  }
 223 @@ -789,8 +789,8 @@ static int mtk_infrasys_init(struct plat
 224                 }
 225         }
 226
 227 -       mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 228 -                                               infra_clk_data);
 229 +       mtk_clk_register_gates(&pdev->dev, node, infra_clks,
 230 +                              ARRAY_SIZE(infra_clks), infra_clk_data);
 231         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 232                                                 infra_clk_data);
 233
 234 @@ -902,8 +902,8 @@ static int mtk_pericfg_init(struct platf
 235         if (!clk_data)
 236                 return -ENOMEM;
 237
 238 -       mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
 239 -                                               clk_data);
 240 +       mtk_clk_register_gates(&pdev->dev, node, peri_clks,
 241 +                              ARRAY_SIZE(peri_clks), clk_data);
 242
 243         mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
 244                         &mt2701_clk_lock, clk_data);
 245 --- a/drivers/clk/mediatek/clk-mt2712-mm.c
 246 +++ b/drivers/clk/mediatek/clk-mt2712-mm.c
 247 @@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl
 248
 249         clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
 250
 251 -       mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
 252 -                       clk_data);
 253 +       mtk_clk_register_gates(&pdev->dev, node, mm_clks,
 254 +                              ARRAY_SIZE(mm_clks), clk_data);
 255
 256         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 257
 258 --- a/drivers/clk/mediatek/clk-mt2712.c
 259 +++ b/drivers/clk/mediatek/clk-mt2712.c
 260 @@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p
 261                         &mt2712_clk_lock, top_clk_data);
 262         mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
 263                         &mt2712_clk_lock, top_clk_data);
 264 -       mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
 265 -                       top_clk_data);
 266 +       mtk_clk_register_gates(&pdev->dev, node, top_clks,
 267 +                              ARRAY_SIZE(top_clks), top_clk_data);
 268
 269         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
 270
 271 @@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct
 272
 273         clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
 274
 275 -       mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 276 -                       clk_data);
 277 +       mtk_clk_register_gates(&pdev->dev, node, infra_clks,
 278 +                              ARRAY_SIZE(infra_clks), clk_data);
 279
 280         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 281
 282 @@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct
 283
 284         clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
 285
 286 -       mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
 287 -                       clk_data);
 288 +       mtk_clk_register_gates(&pdev->dev, node, peri_clks,
 289 +                              ARRAY_SIZE(peri_clks), clk_data);
 290
 291         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 292
 293 --- a/drivers/clk/mediatek/clk-mt7622-aud.c
 294 +++ b/drivers/clk/mediatek/clk-mt7622-aud.c
 295 @@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru
 296
 297         clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
 298
 299 -       mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
 300 -                              clk_data);
 301 +       mtk_clk_register_gates(&pdev->dev, node, audio_clks,
 302 +                              ARRAY_SIZE(audio_clks), clk_data);
 303
 304         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 305         if (r) {
 306 --- a/drivers/clk/mediatek/clk-mt7622-eth.c
 307 +++ b/drivers/clk/mediatek/clk-mt7622-eth.c
 308 @@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct
 309
 310         clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
 311
 312 -       mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
 313 -                              clk_data);
 314 +       mtk_clk_register_gates(&pdev->dev, node, eth_clks,
 315 +                              ARRAY_SIZE(eth_clks), clk_data);
 316
 317         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 318         if (r)
 319 @@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru
 320
 321         clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
 322
 323 -       mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
 324 -                              clk_data);
 325 +       mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
 326 +                              ARRAY_SIZE(sgmii_clks), clk_data);
 327
 328         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 329         if (r)
 330 --- a/drivers/clk/mediatek/clk-mt7622-hif.c
 331 +++ b/drivers/clk/mediatek/clk-mt7622-hif.c
 332 @@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru
 333
 334         clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
 335
 336 -       mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
 337 -                              clk_data);
 338 +       mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
 339 +                              ARRAY_SIZE(ssusb_clks), clk_data);
 340
 341         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 342         if (r)
 343 @@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc
 344
 345         clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
 346
 347 -       mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
 348 -                              clk_data);
 349 +       mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
 350 +                              ARRAY_SIZE(pcie_clks), clk_data);
 351
 352         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 353         if (r)
 354 --- a/drivers/clk/mediatek/clk-mt7622.c
 355 +++ b/drivers/clk/mediatek/clk-mt7622.c
 356 @@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat
 357         mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
 358                                   base, &mt7622_clk_lock, clk_data);
 359
 360 -       mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
 361 -                              clk_data);
 362 +       mtk_clk_register_gates(&pdev->dev, node, top_clks,
 363 +                              ARRAY_SIZE(top_clks), clk_data);
 364
 365         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 366  }
 367 @@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat
 368
 369         clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
 370
 371 -       mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 372 -                              clk_data);
 373 +       mtk_clk_register_gates(&pdev->dev, node, infra_clks,
 374 +                              ARRAY_SIZE(infra_clks), clk_data);
 375
 376         mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
 377                                   clk_data);
 378 @@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl
 379         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
 380                               clk_data);
 381
 382 -       mtk_clk_register_gates(node, apmixed_clks,
 383 +       mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
 384                                ARRAY_SIZE(apmixed_clks), clk_data);
 385
 386         return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 387 @@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf
 388
 389         clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
 390
 391 -       mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
 392 -                              clk_data);
 393 +       mtk_clk_register_gates(&pdev->dev, node, peri_clks,
 394 +                              ARRAY_SIZE(peri_clks), clk_data);
 395
 396         mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
 397                                     &mt7622_clk_lock, clk_data);
 398 --- a/drivers/clk/mediatek/clk-mt7629-eth.c
 399 +++ b/drivers/clk/mediatek/clk-mt7629-eth.c
 400 @@ -82,7 +82,8 @@ static int clk_mt7629_ethsys_init(struct
 401         if (!clk_data)
 402                 return -ENOMEM;
 403
 404 -       mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
 405 +       mtk_clk_register_gates(&pdev->dev, node, eth_clks,
 406 +                              CLK_ETH_NR_CLK, clk_data);
 407
 408         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 409         if (r)
 410 @@ -106,8 +107,8 @@ static int clk_mt7629_sgmiisys_init(stru
 411         if (!clk_data)
 412                 return -ENOMEM;
 413
 414 -       mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
 415 -                              clk_data);
 416 +       mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
 417 +                              CLK_SGMII_NR_CLK, clk_data);
 418
 419         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 420         if (r)
 421 --- a/drivers/clk/mediatek/clk-mt7629-hif.c
 422 +++ b/drivers/clk/mediatek/clk-mt7629-hif.c
 423 @@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru
 424
 425         clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
 426
 427 -       mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
 428 -                              clk_data);
 429 +       mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
 430 +                              ARRAY_SIZE(ssusb_clks), clk_data);
 431
 432         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 433         if (r)
 434 @@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc
 435
 436         clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
 437
 438 -       mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
 439 -                              clk_data);
 440 +       mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
 441 +                              ARRAY_SIZE(pcie_clks), clk_data);
 442
 443         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 444         if (r)
 445 --- a/drivers/clk/mediatek/clk-mt7629.c
 446 +++ b/drivers/clk/mediatek/clk-mt7629.c
 447 @@ -585,8 +585,8 @@ static int mtk_infrasys_init(struct plat
 448         if (!clk_data)
 449                 return -ENOMEM;
 450
 451 -       mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 452 -                              clk_data);
 453 +       mtk_clk_register_gates(&pdev->dev, node, infra_clks,
 454 +                              ARRAY_SIZE(infra_clks), clk_data);
 455
 456         mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
 457                                   clk_data);
 458 @@ -610,8 +610,8 @@ static int mtk_pericfg_init(struct platf
 459         if (!clk_data)
 460                 return -ENOMEM;
 461
 462 -       mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
 463 -                              clk_data);
 464 +       mtk_clk_register_gates(&pdev->dev, node, peri_clks,
 465 +                              ARRAY_SIZE(peri_clks), clk_data);
 466
 467         mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
 468                                     &mt7629_clk_lock, clk_data);
 469 @@ -637,7 +637,7 @@ static int mtk_apmixedsys_init(struct pl
 470         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
 471                               clk_data);
 472
 473 -       mtk_clk_register_gates(node, apmixed_clks,
 474 +       mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
 475                                ARRAY_SIZE(apmixed_clks), clk_data);
 476
 477         clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
 478 --- a/drivers/clk/mediatek/clk-mt7986-eth.c
 479 +++ b/drivers/clk/mediatek/clk-mt7986-eth.c
 480 @@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s
 481
 482         clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
 483
 484 -       mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
 485 -                              clk_data);
 486 +       mtk_clk_register_gates(NULL, node, sgmii0_clks,
 487 +                              ARRAY_SIZE(sgmii0_clks), clk_data);
 488
 489         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 490         if (r)
 491 @@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s
 492
 493         clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
 494
 495 -       mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
 496 -                              clk_data);
 497 +       mtk_clk_register_gates(NULL, node, sgmii1_clks,
 498 +                              ARRAY_SIZE(sgmii1_clks), clk_data);
 499
 500         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 501
 502 @@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc
 503
 504         clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
 505
 506 -       mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
 507 +       mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
 508
 509         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 510
 511 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
 512 +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
 513 @@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str
 514         mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
 515         mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
 516                                &mt7986_clk_lock, clk_data);
 517 -       mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 518 -                              clk_data);
 519 +       mtk_clk_register_gates(&pdev->dev, node, infra_clks,
 520 +                              ARRAY_SIZE(infra_clks), clk_data);
 521
 522         r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 523         if (r) {
 524 --- a/drivers/clk/mediatek/clk-mtk.c
 525 +++ b/drivers/clk/mediatek/clk-mtk.c
 526 @@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform
 527         if (!clk_data)
 528                 return -ENOMEM;
 529
 530 -       r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks,
 531 -                                           clk_data, &pdev->dev);
 532 +       r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
 533 +                                  clk_data);
 534         if (r)
 535                 goto free_data;
 536