target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License
   4  * as published by the Free Software Foundation; either version 2
   5  * of the License, or (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/delay.h>
  19 #include <linux/of_mdio.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_gpio.h>
  22
  23
  24 #include  "./rtl8367c/include/rtk_switch.h"
  25 #include  "./rtl8367c/include/port.h"
  26 #include  "./rtl8367c/include/vlan.h"
  27 #include  "./rtl8367c/include/rtl8367c_asicdrv_port.h"
  28
  29 struct rtk_gsw {
  30         struct device           *dev;
  31         struct mii_bus          *bus;
  32         int reset_pin;
  33 };
  34
  35 static struct rtk_gsw *_gsw;
  36
  37 extern int gsw_debug_proc_init(void);
  38 extern void gsw_debug_proc_exit(void);
  39
  40 #ifdef CONFIG_SWCONFIG
  41 extern int rtl8367s_swconfig_init( void (*reset_func)(void) );
  42 #endif
  43
  44 /*mii_mgr_read/mii_mgr_write is the callback API for rtl8367 driver*/
  45 unsigned int mii_mgr_read(unsigned int phy_addr,unsigned int phy_register,unsigned int *read_data)
  46 {
  47         struct mii_bus *bus = _gsw->bus;
  48
  49         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
  50
  51         *read_data = bus->read(bus, phy_addr, phy_register);
  52
  53         mutex_unlock(&bus->mdio_lock);
  54
  55         return 0;
  56 }
  57
  58 unsigned int mii_mgr_write(unsigned int phy_addr,unsigned int phy_register,unsigned int write_data)
  59 {
  60         struct mii_bus *bus =  _gsw->bus;
  61
  62         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
  63
  64         bus->write(bus, phy_addr, phy_register, write_data);
  65
  66         mutex_unlock(&bus->mdio_lock);
  67
  68         return 0;
  69 }
  70
  71 static int rtl8367s_hw_reset(void)
  72 {
  73         struct rtk_gsw *gsw = _gsw;
  74
  75         if (gsw->reset_pin < 0)
  76                 return 0;
  77
  78         gpio_direction_output(gsw->reset_pin, 0);
  79
  80         usleep_range(1000, 1100);
  81
  82         gpio_set_value(gsw->reset_pin, 1);
  83
  84         mdelay(500);
  85
  86         return 0;
  87 }
  88
  89 static int rtl8367s_vlan_config(int want_at_p0)
  90 {
  91         rtk_vlan_cfg_t vlan1, vlan2;
  92
  93         /* Set LAN/WAN VLAN partition */
  94         memset(&vlan1, 0x00, sizeof(rtk_vlan_cfg_t));
  95
  96         RTK_PORTMASK_PORT_SET(vlan1.mbr, EXT_PORT0);
  97         RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT1);
  98         RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT2);
  99         RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT3);
 100         RTK_PORTMASK_PORT_SET(vlan1.untag, EXT_PORT0);
 101         RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT1);
 102         RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT2);
 103         RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT3);
 104
 105          if (want_at_p0) {
 106                 RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT4);
 107                 RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT4);
 108         } else {
 109                 RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT0);
 110                 RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT0);
 111         }
 112
 113         vlan1.ivl_en = 1;
 114
 115         rtk_vlan_set(1, &vlan1);
 116
 117         memset(&vlan2, 0x00, sizeof(rtk_vlan_cfg_t));
 118
 119         RTK_PORTMASK_PORT_SET(vlan2.mbr, EXT_PORT1);
 120         RTK_PORTMASK_PORT_SET(vlan2.untag, EXT_PORT1);
 121
 122         if (want_at_p0) {
 123                 RTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT0);
 124                 RTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT0);
 125         } else {
 126                 RTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT4);
 127                 RTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT4);
 128         }
 129
 130         vlan2.ivl_en = 1;
 131         rtk_vlan_set(2, &vlan2);
 132
 133         rtk_vlan_portPvid_set(EXT_PORT0, 1, 0);
 134         rtk_vlan_portPvid_set(UTP_PORT1, 1, 0);
 135         rtk_vlan_portPvid_set(UTP_PORT2, 1, 0);
 136         rtk_vlan_portPvid_set(UTP_PORT3, 1, 0);
 137         rtk_vlan_portPvid_set(EXT_PORT1, 2, 0);
 138
 139         if (want_at_p0) {
 140                 rtk_vlan_portPvid_set(UTP_PORT0, 2, 0);
 141                 rtk_vlan_portPvid_set(UTP_PORT4, 1, 0);
 142         } else {
 143                 rtk_vlan_portPvid_set(UTP_PORT0, 1, 0);
 144                 rtk_vlan_portPvid_set(UTP_PORT4, 2, 0);
 145         }
 146
 147         return 0;
 148 }
 149
 150 static int rtl8367s_hw_init(void)
 151 {
 152
 153         rtl8367s_hw_reset();
 154
 155         if(rtk_switch_init())
 156                 return -1;
 157
 158         mdelay(500);
 159
 160         if (rtk_vlan_reset())
 161                 return -1;
 162
 163         if (rtk_vlan_init())
 164                 return -1;
 165
 166         return 0;
 167 }
 168
 169 static void set_rtl8367s_sgmii(void)
 170 {
 171         rtk_port_mac_ability_t mac_cfg;
 172         rtk_mode_ext_t mode;
 173
 174         mode = MODE_EXT_HSGMII;
 175         mac_cfg.forcemode = MAC_FORCE;
 176         mac_cfg.speed = PORT_SPEED_2500M;
 177         mac_cfg.duplex = PORT_FULL_DUPLEX;
 178         mac_cfg.link = PORT_LINKUP;
 179         mac_cfg.nway = DISABLED;
 180         mac_cfg.txpause = ENABLED;
 181         mac_cfg.rxpause = ENABLED;
 182         rtk_port_macForceLinkExt_set(EXT_PORT0, mode, &mac_cfg);
 183         rtk_port_sgmiiNway_set(EXT_PORT0, DISABLED);
 184         rtk_port_phyEnableAll_set(ENABLED);
 185
 186 }
 187
 188 static void set_rtl8367s_rgmii(void)
 189 {
 190         rtk_port_mac_ability_t mac_cfg;
 191         rtk_mode_ext_t mode;
 192
 193         mode = MODE_EXT_RGMII;
 194         mac_cfg.forcemode = MAC_FORCE;
 195         mac_cfg.speed = PORT_SPEED_1000M;
 196         mac_cfg.duplex = PORT_FULL_DUPLEX;
 197         mac_cfg.link = PORT_LINKUP;
 198         mac_cfg.nway = DISABLED;
 199         mac_cfg.txpause = ENABLED;
 200         mac_cfg.rxpause = ENABLED;
 201         rtk_port_macForceLinkExt_set(EXT_PORT1, mode, &mac_cfg);
 202         rtk_port_rgmiiDelayExt_set(EXT_PORT1, 1, 3);
 203         rtk_port_phyEnableAll_set(ENABLED);
 204
 205 }
 206
 207 void init_gsw(void)
 208 {
 209         rtl8367s_hw_init();
 210         set_rtl8367s_sgmii();
 211         set_rtl8367s_rgmii();
 212 }
 213
 214 // bleow are platform driver
 215 static const struct of_device_id rtk_gsw_match[] = {
 216         { .compatible = "mediatek,rtk-gsw" },
 217         {},
 218 };
 219
 220 MODULE_DEVICE_TABLE(of, rtk_gsw_match);
 221
 222 static int rtk_gsw_probe(struct platform_device *pdev)
 223 {
 224         struct device_node *np = pdev->dev.of_node;
 225         struct device_node *mdio;
 226         struct mii_bus *mdio_bus;
 227         struct rtk_gsw *gsw;
 228         const char *pm;
 229         int ret;
 230
 231         mdio = of_parse_phandle(np, "mediatek,mdio", 0);
 232
 233         if (!mdio)
 234                 return -EINVAL;
 235
 236         mdio_bus = of_mdio_find_bus(mdio);
 237
 238         if (!mdio_bus)
 239                 return -EPROBE_DEFER;
 240
 241         gsw = devm_kzalloc(&pdev->dev, sizeof(struct rtk_gsw), GFP_KERNEL);
 242
 243         if (!gsw)
 244                 return -ENOMEM;
 245
 246         gsw->dev = &pdev->dev;
 247
 248         gsw->bus = mdio_bus;
 249
 250         gsw->reset_pin = of_get_named_gpio(np, "mediatek,reset-pin", 0);
 251         if (gsw->reset_pin >= 0) {
 252                 ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mediatek,reset-pin");
 253                 if (ret)
 254                         printk("fail to devm_gpio_request\n");
 255         }
 256
 257         _gsw = gsw;
 258
 259         init_gsw();
 260
 261         //init default vlan or init swocnfig
 262         if(!of_property_read_string(pdev->dev.of_node,
 263                                                 "mediatek,port_map", &pm)) {
 264
 265                 if (!strcasecmp(pm, "wllll"))
 266                         rtl8367s_vlan_config(1);
 267                 else
 268                         rtl8367s_vlan_config(0);
 269
 270                 } else {
 271 #ifdef CONFIG_SWCONFIG
 272                 rtl8367s_swconfig_init(&init_gsw);
 273 #else
 274                 rtl8367s_vlan_config(0);
 275 #endif
 276         }
 277
 278         gsw_debug_proc_init();
 279
 280         platform_set_drvdata(pdev, gsw);
 281
 282         return 0;
 283
 284 }
 285
 286 static int rtk_gsw_remove(struct platform_device *pdev)
 287 {
 288         platform_set_drvdata(pdev, NULL);
 289         gsw_debug_proc_exit();
 290
 291         return 0;
 292 }
 293
 294 static struct platform_driver gsw_driver = {
 295         .probe = rtk_gsw_probe,
 296         .remove = rtk_gsw_remove,
 297         .driver = {
 298                 .name = "rtk-gsw",
 299                 .owner = THIS_MODULE,
 300                 .of_match_table = rtk_gsw_match,
 301         },
 302 };
 303
 304 module_platform_driver(gsw_driver);
 305
 306 MODULE_LICENSE("GPL");
 307 MODULE_AUTHOR("Mark Lee <marklee0201@gmail.com>");
 308 MODULE_DESCRIPTION("rtl8367c switch driver for MT7622");
 309