target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "MediaTek MT7622 RFB1 board";
  18         compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
  19
  20         aliases {
  21                 serial0 = &uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  27         };
  28
  29         cpus {
  30                 cpu@0 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34
  35                 cpu@1 {
  36                         proc-supply = <&mt6380_vcpu_reg>;
  37                         sram-supply = <&mt6380_vm_reg>;
  38                 };
  39         };
  40
  41         gpio-keys {
  42                 compatible = "gpio-keys";
  43                 poll-interval = <100>;
  44
  45                 factory {
  46                         label = "factory";
  47                         linux,code = <BTN_0>;
  48                         gpios = <&pio 0 0>;
  49                 };
  50
  51                 wps {
  52                         label = "wps";
  53                         linux,code = <KEY_WPS_BUTTON>;
  54                         gpios = <&pio 102 0>;
  55                 };
  56         };
  57
  58         memory {
  59                 reg = <0 0x40000000 0 0x3F000000>;
  60         };
  61
  62         reg_1p8v: regulator-1p8v {
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "fixed-1.8V";
  65                 regulator-min-microvolt = <1800000>;
  66                 regulator-max-microvolt = <1800000>;
  67                 regulator-always-on;
  68         };
  69
  70         reg_3p3v: regulator-3p3v {
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "fixed-3.3V";
  73                 regulator-min-microvolt = <3300000>;
  74                 regulator-max-microvolt = <3300000>;
  75                 regulator-boot-on;
  76                 regulator-always-on;
  77         };
  78
  79         reg_5v: regulator-5v {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "fixed-5V";
  82                 regulator-min-microvolt = <5000000>;
  83                 regulator-max-microvolt = <5000000>;
  84                 regulator-boot-on;
  85                 regulator-always-on;
  86         };
  87
  88         rtkgsw: rtkgsw@0 {
  89                 compatible = "mediatek,rtk-gsw";
  90                 mediatek,ethsys = <&ethsys>;
  91                 mediatek,mdio = <&mdio>;
  92                 mediatek,reset-pin = <&pio 54 0>;
  93                 status = "okay";
  94         };
  95 };
  96
  97 &pcie {
  98         pinctrl-names = "default", "pcie1_pins";
  99         pinctrl-0 = <&pcie0_pins>;
 100         pinctrl-1 = <&pcie1_pins>;
 101         status = "okay";
 102
 103         pcie@0,0 {
 104                 status = "okay";
 105         };
 106
 107         pcie@1,0 {
 108                 status = "okay";
 109         };
 110
 111 };
 112
 113 &pio {
 114         /* eMMC is shared pin with parallel NAND */
 115         emmc_pins_default: emmc-pins-default {
 116                 mux {
 117                         function = "emmc", "emmc_rst";
 118                         groups = "emmc";
 119                 };
 120
 121                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 122                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 123                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 124                  */
 125                 conf-cmd-dat {
 126                         pins = "NDL0", "NDL1", "NDL2",
 127                                "NDL3", "NDL4", "NDL5",
 128                                "NDL6", "NDL7", "NRB";
 129                         input-enable;
 130                         bias-pull-up;
 131                 };
 132
 133                 conf-clk {
 134                         pins = "NCLE";
 135                         bias-pull-down;
 136                 };
 137         };
 138
 139         emmc_pins_uhs: emmc-pins-uhs {
 140                 mux {
 141                         function = "emmc";
 142                         groups = "emmc";
 143                 };
 144
 145                 conf-cmd-dat {
 146                         pins = "NDL0", "NDL1", "NDL2",
 147                                "NDL3", "NDL4", "NDL5",
 148                                "NDL6", "NDL7", "NRB";
 149                         input-enable;
 150                         drive-strength = <4>;
 151                         bias-pull-up;
 152                 };
 153
 154                 conf-clk {
 155                         pins = "NCLE";
 156                         drive-strength = <4>;
 157                         bias-pull-down;
 158                 };
 159         };
 160
 161         eth_pins: eth-pins {
 162                 mux {
 163                         function = "eth";
 164                         groups = "mdc_mdio", "rgmii_via_gmac2";
 165                 };
 166         };
 167
 168         i2c1_pins: i2c1-pins {
 169                 mux {
 170                         function = "i2c";
 171                         groups =  "i2c1_0";
 172                 };
 173         };
 174
 175         i2c2_pins: i2c2-pins {
 176                 mux {
 177                         function = "i2c";
 178                         groups =  "i2c2_0";
 179                 };
 180         };
 181
 182         i2s1_pins: i2s1-pins {
 183                 mux {
 184                         function = "i2s";
 185                         groups =  "i2s_out_mclk_bclk_ws",
 186                                   "i2s1_in_data",
 187                                   "i2s1_out_data";
 188                 };
 189
 190                 conf {
 191                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 192                                "I2S_WS", "I2S_MCLK";
 193                         drive-strength = <12>;
 194                         bias-pull-down;
 195                 };
 196         };
 197
 198         irrx_pins: irrx-pins {
 199                 mux {
 200                         function = "ir";
 201                         groups =  "ir_1_rx";
 202                 };
 203         };
 204
 205         irtx_pins: irtx-pins {
 206                 mux {
 207                         function = "ir";
 208                         groups =  "ir_1_tx";
 209                 };
 210         };
 211
 212         /* Parallel nand is shared pin with eMMC */
 213         parallel_nand_pins: parallel-nand-pins {
 214                 mux {
 215                         function = "flash";
 216                         groups = "par_nand";
 217                 };
 218         };
 219
 220         pcie0_pins: pcie0-pins {
 221                 mux {
 222                         function = "pcie";
 223                         groups = "pcie0_pad_perst",
 224                                  "pcie0_1_waken",
 225                                  "pcie0_1_clkreq";
 226                 };
 227         };
 228
 229         pcie1_pins: pcie1-pins {
 230                 mux {
 231                         function = "pcie";
 232                         groups = "pcie1_pad_perst",
 233                                  "pcie1_0_waken",
 234                                  "pcie1_0_clkreq";
 235                 };
 236         };
 237
 238         pmic_bus_pins: pmic-bus-pins {
 239                 mux {
 240                         function = "pmic";
 241                         groups = "pmic_bus";
 242                 };
 243         };
 244
 245         pwm7_pins: pwm1-2-pins {
 246                 mux {
 247                         function = "pwm";
 248                         groups = "pwm_ch7_2";
 249                 };
 250         };
 251
 252         wled_pins: wled-pins {
 253                 mux {
 254                         function = "led";
 255                         groups = "wled";
 256                 };
 257         };
 258
 259         sd0_pins_default: sd0-pins-default {
 260                 mux {
 261                         function = "sd";
 262                         groups = "sd_0";
 263                 };
 264
 265                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 266                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 267                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 268                  */
 269                 conf-cmd-data {
 270                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 271                                "I2S2_IN","I2S4_OUT";
 272                         input-enable;
 273                         drive-strength = <8>;
 274                         bias-pull-up;
 275                 };
 276                 conf-clk {
 277                         pins = "I2S3_OUT";
 278                         drive-strength = <12>;
 279                         bias-pull-down;
 280                 };
 281                 conf-cd {
 282                         pins = "TXD3";
 283                         bias-pull-up;
 284                 };
 285         };
 286
 287         sd0_pins_uhs: sd0-pins-uhs {
 288                 mux {
 289                         function = "sd";
 290                         groups = "sd_0";
 291                 };
 292
 293                 conf-cmd-data {
 294                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 295                                "I2S2_IN","I2S4_OUT";
 296                         input-enable;
 297                         bias-pull-up;
 298                 };
 299
 300                 conf-clk {
 301                         pins = "I2S3_OUT";
 302                         bias-pull-down;
 303                 };
 304         };
 305
 306         /* Serial NAND is shared pin with SPI-NOR */
 307         serial_nand_pins: serial-nand-pins {
 308                 mux {
 309                         function = "flash";
 310                         groups = "snfi";
 311                 };
 312         };
 313
 314         spic0_pins: spic0-pins {
 315                 mux {
 316                         function = "spi";
 317                         groups = "spic0_0";
 318                 };
 319         };
 320
 321         spic1_pins: spic1-pins {
 322                 mux {
 323                         function = "spi";
 324                         groups = "spic1_0";
 325                 };
 326         };
 327
 328         /* SPI-NOR is shared pin with serial NAND */
 329         spi_nor_pins: spi-nor-pins {
 330                 mux {
 331                         function = "flash";
 332                         groups = "spi_nor";
 333                 };
 334         };
 335
 336         /* serial NAND is shared pin with SPI-NOR */
 337         serial_nand_pins: serial-nand-pins {
 338                 mux {
 339                         function = "flash";
 340                         groups = "snfi";
 341                 };
 342         };
 343
 344         uart0_pins: uart0-pins {
 345                 mux {
 346                         function = "uart";
 347                         groups = "uart0_0_tx_rx" ;
 348                 };
 349         };
 350
 351         uart2_pins: uart2-pins {
 352                 mux {
 353                         function = "uart";
 354                         groups = "uart2_1_tx_rx" ;
 355                 };
 356         };
 357
 358         watchdog_pins: watchdog-pins {
 359                 mux {
 360                         function = "watchdog";
 361                         groups = "watchdog";
 362                 };
 363         };
 364 };
 365
 366 &bch {
 367         status = "okay";
 368 };
 369
 370 &btif {
 371         status = "okay";
 372 };
 373
 374 &cir {
 375         pinctrl-names = "default";
 376         pinctrl-0 = <&irrx_pins>;
 377         status = "okay";
 378 };
 379
 380 &eth {
 381         status = "okay";
 382         gmac0: mac@0 {
 383                 compatible = "mediatek,eth-mac";
 384                 reg = <0>;
 385                 phy-mode = "sgmii";
 386                 fixed-link {
 387                         speed = <1000>;
 388                         full-duplex;
 389                         pause;
 390                 };
 391         };
 392         gmac1: mac@1 {
 393                 compatible = "mediatek,eth-mac";
 394                 reg = <1>;
 395                 phy-mode = "rgmii";
 396                 fixed-link {
 397                         speed = <1000>;
 398                         full-duplex;
 399                         pause;
 400                 };
 401         };
 402         mdio: mdio-bus {
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405         };
 406 };
 407
 408 &i2c1 {
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&i2c1_pins>;
 411         status = "okay";
 412 };
 413
 414 &i2c2 {
 415         pinctrl-names = "default";
 416         pinctrl-0 = <&i2c2_pins>;
 417         status = "okay";
 418 };
 419
 420 &mmc0 {
 421         pinctrl-names = "default", "state_uhs";
 422         pinctrl-0 = <&emmc_pins_default>;
 423         pinctrl-1 = <&emmc_pins_uhs>;
 424         status = "okay";
 425         bus-width = <8>;
 426         max-frequency = <50000000>;
 427         cap-mmc-highspeed;
 428         mmc-hs200-1_8v;
 429         vmmc-supply = <&reg_3p3v>;
 430         vqmmc-supply = <&reg_1p8v>;
 431         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 432         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 433         non-removable;
 434 };
 435
 436 &mmc1 {
 437         pinctrl-names = "default", "state_uhs";
 438         pinctrl-0 = <&sd0_pins_default>;
 439         pinctrl-1 = <&sd0_pins_uhs>;
 440         status = "okay";
 441         bus-width = <4>;
 442         max-frequency = <50000000>;
 443         cap-sd-highspeed;
 444         r_smpl = <1>;
 445         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 446         vmmc-supply = <&reg_3p3v>;
 447         vqmmc-supply = <&reg_3p3v>;
 448         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 449         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 450 };
 451
 452 &nandc {
 453         pinctrl-names = "default";
 454         pinctrl-0 = <&parallel_nand_pins>;
 455         status = "disabled";
 456 };
 457
 458 &nor_flash {
 459         pinctrl-names = "default";
 460         pinctrl-0 = <&spi_nor_pins>;
 461         status = "disabled";
 462
 463         flash@0 {
 464                 compatible = "jedec,spi-nor";
 465                 reg = <0>;
 466         };
 467 };
 468
 469 &pwm {
 470         pinctrl-names = "default";
 471         pinctrl-0 = <&pwm7_pins>;
 472         status = "okay";
 473 };
 474
 475 &pwrap {
 476         pinctrl-names = "default";
 477         pinctrl-0 = <&pmic_bus_pins>;
 478
 479         status = "okay";
 480 };
 481
 482 &snfi {
 483         pinctrl-names = "default";
 484         pinctrl-0 = <&serial_nand_pins>;
 485         status = "okay";
 486
 487         spi_nand@0 {
 488                 #address-cells = <1>;
 489                 #size-cells = <1>;
 490                 compatible = "spi-nand";
 491                 spi-max-frequency = <104000000>;
 492                 reg = <0>;
 493
 494                 partitions {
 495                         compatible = "fixed-partitions";
 496                         #address-cells = <1>;
 497                         #size-cells = <1>;
 498
 499                         partition@0 {
 500                                 label = "Preloader";
 501                                 reg = <0x00000 0x0080000>;
 502                                 read-only;
 503                         };
 504
 505                         partition@80000 {
 506                                 label = "ATF";
 507                                 reg = <0x80000 0x0040000>;
 508                         };
 509
 510                         partition@c0000 {
 511                                 label = "Bootloader";
 512                                 reg = <0xc0000 0x0080000>;
 513                         };
 514
 515                         partition@140000 {
 516                                 label = "Config";
 517                                 reg = <0x140000 0x0080000>;
 518                         };
 519
 520                         partition@1c0000 {
 521                                 label = "Factory";
 522                                 reg = <0x1c0000 0x0040000>;
 523                         };
 524
 525                         partition@200000 {
 526                                 label = "Kernel";
 527                                 reg = <0x200000 0x2000000>;
 528                         };
 529
 530                         partition@2200000 {
 531                                 label = "User_data";
 532                                 reg = <0x2200000 0x4000000>;
 533                         };
 534                 };
 535         };
 536 };
 537
 538 &spi0 {
 539         pinctrl-names = "default";
 540         pinctrl-0 = <&spic0_pins>;
 541         status = "okay";
 542 };
 543
 544 &spi1 {
 545         pinctrl-names = "default";
 546         pinctrl-0 = <&spic1_pins>;
 547         status = "okay";
 548 };
 549
 550 &ssusb {
 551         vusb33-supply = <&reg_3p3v>;
 552         vbus-supply = <&reg_5v>;
 553         status = "okay";
 554 };
 555
 556 &u3phy {
 557         status = "okay";
 558 };
 559
 560 &uart0 {
 561         pinctrl-names = "default";
 562         pinctrl-0 = <&uart0_pins>;
 563         status = "okay";
 564 };
 565
 566 &uart2 {
 567         pinctrl-names = "default";
 568         pinctrl-0 = <&uart2_pins>;
 569         status = "okay";
 570 };
 571
 572 &watchdog {
 573         pinctrl-names = "default";
 574         pinctrl-0 = <&watchdog_pins>;
 575         status = "okay";
 576 };