target/linux/layerscape/patches-5.4/701-net-0305-staging-fsl_ppfe-eth-replace-magic-numbers.patch

   1 From cdebdc900ae5cb29dc1cce1c26865001534ab77d Mon Sep 17 00:00:00 2001
   2 From: Calvin Johnson <calvin.johnson@nxp.com>
   3 Date: Thu, 4 Oct 2018 09:38:34 +0530
   4 Subject: [PATCH] staging: fsl_ppfe/eth: replace magic numbers
   5
   6 Replace magic numbers and some cosmetic changes.
   7
   8 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
   9 ---
  10  drivers/staging/fsl_ppfe/pfe_eth.c | 83 ++++++++++++++++++++++++++++----------
  11  1 file changed, 61 insertions(+), 22 deletions(-)
  12
  13 --- a/drivers/staging/fsl_ppfe/pfe_eth.c
  14 +++ b/drivers/staging/fsl_ppfe/pfe_eth.c
  15 @@ -66,6 +66,36 @@ static void pfe_eth_flush_tx(struct pfe_
  16  static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int
  17                                 from_tx, int n_desc);
  18
  19 +/* MDIO registers */
  20 +#define MDIO_SGMII_CR                  0x00
  21 +#define MDIO_SGMII_SR                  0x01
  22 +#define MDIO_SGMII_DEV_ABIL_SGMII      0x04
  23 +#define MDIO_SGMII_LINK_TMR_L          0x12
  24 +#define MDIO_SGMII_LINK_TMR_H          0x13
  25 +#define MDIO_SGMII_IF_MODE             0x14
  26 +
  27 +/* SGMII Control defines */
  28 +#define SGMII_CR_RST                   0x8000
  29 +#define SGMII_CR_AN_EN                 0x1000
  30 +#define SGMII_CR_RESTART_AN            0x0200
  31 +#define SGMII_CR_FD                    0x0100
  32 +#define SGMII_CR_SPEED_SEL1_1G         0x0040
  33 +#define SGMII_CR_DEF_VAL               (SGMII_CR_AN_EN | SGMII_CR_FD | \
  34 +                                        SGMII_CR_SPEED_SEL1_1G)
  35 +
  36 +/* SGMII IF Mode */
  37 +#define SGMII_DUPLEX_HALF              0x10
  38 +#define SGMII_SPEED_10MBPS             0x00
  39 +#define SGMII_SPEED_100MBPS            0x04
  40 +#define SGMII_SPEED_1GBPS              0x08
  41 +#define SGMII_USE_SGMII_AN             0x02
  42 +#define SGMII_EN                       0x01
  43 +
  44 +/* SGMII Device Ability for SGMII */
  45 +#define SGMII_DEV_ABIL_ACK             0x4000
  46 +#define SGMII_DEV_ABIL_EEE_CLK_STP_EN  0x0100
  47 +#define SGMII_DEV_ABIL_SGMII           0x0001
  48 +
  49  unsigned int gemac_regs[] = {
  50         0x0004, /* Interrupt event */
  51         0x0008, /* Interrupt mask */
  52 @@ -1042,6 +1072,10 @@ static int pfe_get_phydev_speed(struct p
  53  #define SCFG_RGMIIPCR_SETSP_10M         (0x00000002)
  54  #define SCFG_RGMIIPCR_SETFD             (0x00000001)
  55
  56 +#define MDIOSELCR      0x484
  57 +#define MDIOSEL_SERDES 0x0
  58 +#define MDIOSEL_EXTPHY  0x80000000
  59 +
  60  static void pfe_set_rgmii_speed(struct phy_device *phydev)
  61  {
  62         u32 rgmii_pcr;
  63 @@ -1187,25 +1221,34 @@ static void ls1012a_configure_serdes(str
  64         netif_info(priv, drv, ndev, "%s\n", __func__);
  65         /* PCS configuration done with corresponding GEMAC */
  66
  67 -       pfe_eth_mdio_read(bus, 0, 0);
  68 -       pfe_eth_mdio_read(bus, 0, 1);
  69 +       pfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR);
  70 +       pfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR);
  71 +
  72 +       pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST);
  73
  74 -       /*These settings taken from validtion team */
  75 -       pfe_eth_mdio_write(bus, 0, 0x0, 0x8000);
  76         if (sgmii_2500) {
  77 -               pfe_eth_mdio_write(bus, 0, 0x14, 0x9);
  78 -               pfe_eth_mdio_write(bus, 0, 0x4, 0x4001);
  79 -               pfe_eth_mdio_write(bus, 0, 0x12, 0xa120);
  80 -               pfe_eth_mdio_write(bus, 0, 0x13, 0x7);
  81 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS
  82 +                                                              | SGMII_EN);
  83 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
  84 +                                  SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII);
  85 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120);
  86 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7);
  87                 /* Autonegotiation need to be disabled for 2.5G SGMII mode*/
  88 -               value = 0x0140;
  89 -               pfe_eth_mdio_write(bus, 0, 0x0, value);
  90 +               value = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
  91 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
  92         } else {
  93 -               pfe_eth_mdio_write(bus, 0, 0x14, 0xb);
  94 -               pfe_eth_mdio_write(bus, 0, 0x4, 0x1a1);
  95 -               pfe_eth_mdio_write(bus, 0, 0x12, 0x400);
  96 -               pfe_eth_mdio_write(bus, 0, 0x13, 0x0);
  97 -               pfe_eth_mdio_write(bus, 0, 0x0, 0x1140);
  98 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE,
  99 +                                  SGMII_SPEED_1GBPS
 100 +                                  | SGMII_USE_SGMII_AN
 101 +                                  | SGMII_EN);
 102 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
 103 +                                  SGMII_DEV_ABIL_EEE_CLK_STP_EN
 104 +                                  | 0xa0
 105 +                                  | SGMII_DEV_ABIL_SGMII);
 106 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400);
 107 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0);
 108 +               value = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
 109 +               pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
 110         }
 111  }
 112
 113 @@ -1235,15 +1278,15 @@ static int pfe_phy_init(struct net_devic
 114             (interface == PHY_INTERFACE_MODE_2500SGMII)) {
 115                 /*Configure SGMII PCS */
 116                 if (pfe->scfg) {
 117 -                       /*Config MDIO from serdes */
 118 -                       regmap_write(pfe->scfg, 0x484, 0x00000000);
 119 +                       /* Config MDIO from serdes */
 120 +                       regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES);
 121                 }
 122                 ls1012a_configure_serdes(ndev);
 123         }
 124
 125         if (pfe->scfg) {
 126                 /*Config MDIO from PAD */
 127 -               regmap_write(pfe->scfg, 0x484, 0x80000000);
 128 +               regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY);
 129         }
 130
 131         priv->oldlink = 0;
 132 @@ -2339,10 +2382,6 @@ static int pfe_eth_init_one(struct pfe *
 133         priv->PHY_baseaddr = cbus_emac_base[0];
 134         priv->GPI_baseaddr = cbus_gpi_base[id];
 135
 136 -#define HIF_GEMAC_TMUQ_BASE    6
 137 -       priv->low_tmu_q =  HIF_GEMAC_TMUQ_BASE + (id * 2);
 138 -       priv->high_tmu_q        =  priv->low_tmu_q + 1;
 139 -
 140         spin_lock_init(&priv->lock);
 141
 142         pfe_eth_fast_tx_timeout_init(priv);