f8b20b0635f2c14f33e1b1e67fb32f32a5d3dd49
[openwrt/staging/stintel.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8064-wpq864.dts
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Christian Mehlis <christian@m3hlis.de>
4 * Copyright (C) 2018 Mathias Kresin <dev@kresin.me>
5 * All rights reserved.
6 */
7
8 #include "qcom-ipq8064-v1.0.dtsi"
9
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/soc/qcom,tcsr.h>
12
13 / {
14 compatible = "compex,wpq864", "qcom,ipq8064";
15 model = "Compex WPQ864";
16
17 aliases {
18 mdio-gpio0 = &mdio0;
19 ethernet0 = &gmac1;
20 ethernet1 = &gmac0;
21
22 led-boot = &led_pass;
23 led-failsafe = &led_fail;
24 led-running = &led_pass;
25 led-upgrade = &led_pass;
26 };
27
28 leds {
29 compatible = "gpio-leds";
30
31 pinctrl-0 = <&led_pins>;
32 pinctrl-names = "default";
33
34 rss4 {
35 label = "green:rss4";
36 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
37 };
38
39 rss3 {
40 label = "green:rss3";
41 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
42 default-state = "keep";
43 };
44
45 rss2 {
46 label = "orange:rss2";
47 gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
48 };
49
50 rss1 {
51 label = "red:rss1";
52 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
53 };
54
55 led_pass: pass {
56 label = "green:pass";
57 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
58 };
59
60 led_fail: fail {
61 label = "green:fail";
62 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
63 };
64
65 usb {
66 label = "green:usb";
67 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
68 };
69
70 usb-pcie {
71 label = "green:usb-pcie";
72 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
73 };
74 };
75
76 keys {
77 compatible = "gpio-keys";
78
79 pinctrl-0 = <&button_pins>;
80 pinctrl-names = "default";
81
82 reset {
83 label = "reset";
84 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
85 linux,code = <KEY_RESTART>;
86 debounce-interval = <60>;
87 wakeup-source;
88 };
89 };
90
91 beeper {
92 compatible = "gpio-beeper";
93
94 pinctrl-0 = <&beeper_pins>;
95 pinctrl-names = "default";
96
97 gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
98 };
99 };
100
101 &rpm {
102 pinctrl-0 = <&rpm_pins>;
103 pinctrl-names = "default";
104 };
105
106 &nand {
107 status = "okay";
108
109 pinctrl-0 = <&nand_pins>;
110 pinctrl-names = "default";
111
112 mt29f2g08abbeah4@0 {
113 compatible = "qcom,nandcs";
114
115 reg = <0>;
116
117 nand-ecc-strength = <4>;
118 nand-bus-width = <8>;
119 nand-ecc-step-size = <512>;
120
121 nand-is-boot-medium;
122 qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
123
124 partitions {
125 compatible = "fixed-partitions";
126 #address-cells = <1>;
127 #size-cells = <1>;
128
129 partition@0 {
130 label = "0:SBL1";
131 reg = <0x0000000 0x0040000>;
132 read-only;
133 };
134
135 partition@40000 {
136 label = "0:MIBIB";
137 reg = <0x0040000 0x0140000>;
138 read-only;
139 };
140
141 partition@180000 {
142 label = "0:SBL2";
143 reg = <0x0180000 0x0140000>;
144 read-only;
145 };
146
147 partition@2c0000 {
148 label = "0:SBL3";
149 reg = <0x02c0000 0x0280000>;
150 read-only;
151 };
152
153 partition@540000 {
154 label = "0:DDRCONFIG";
155 reg = <0x0540000 0x0120000>;
156 read-only;
157 };
158
159 partition@660000 {
160 label = "0:SSD";
161 reg = <0x0660000 0x0120000>;
162 read-only;
163 };
164
165 partition@780000 {
166 label = "0:TZ";
167 reg = <0x0780000 0x0280000>;
168 read-only;
169 };
170
171 partition@a00000 {
172 label = "0:RPM";
173 reg = <0x0a00000 0x0280000>;
174 read-only;
175 };
176
177 partition@c80000 {
178 label = "0:APPSBL";
179 reg = <0x0c80000 0x0500000>;
180 read-only;
181 };
182
183 partition@1180000 {
184 label = "0:APPSBLENV";
185 reg = <0x1180000 0x0080000>;
186 };
187
188 partition@1200000 {
189 label = "0:ART";
190 reg = <0x1200000 0x0140000>;
191 };
192
193 partition@1340000 {
194 label = "ubi";
195 reg = <0x1340000 0x4000000>;
196 };
197
198 partition@5340000 {
199 label = "0:BOOTCONFIG";
200 reg = <0x5340000 0x0060000>;
201 };
202
203 partition@53a0000 {
204 label = "0:SBL2_1";
205 reg = <0x53a0000 0x0140000>;
206 read-only;
207 };
208
209 partition@54e0000 {
210 label = "0:SBL3_1";
211 reg = <0x54e0000 0x0280000>;
212 read-only;
213 };
214
215 partition@5760000 {
216 label = "0:DDRCONFIG_1";
217 reg = <0x5760000 0x0120000>;
218 read-only;
219 };
220
221 partition@5880000 {
222 label = "0:SSD_1";
223 reg = <0x5880000 0x0120000>;
224 read-only;
225 };
226
227 partition@59a0000 {
228 label = "0:TZ_1";
229 reg = <0x59a0000 0x0280000>;
230 read-only;
231 };
232
233 partition@5c20000 {
234 label = "0:RPM_1";
235 reg = <0x5c20000 0x0280000>;
236 read-only;
237 };
238
239 partition@5ea0000 {
240 label = "0:BOOTCONFIG1";
241 reg = <0x5ea0000 0x0060000>;
242 };
243
244 partition@5f00000 {
245 label = "0:APPSBL_1";
246 reg = <0x5f00000 0x0500000>;
247 read-only;
248 };
249
250 partition@6400000 {
251 label = "ubi_1";
252 reg = <0x6400000 0x4000000>;
253 };
254
255 partition@a400000 {
256 label = "unused";
257 reg = <0xa400000 0x5c00000>;
258 };
259 };
260 };
261 };
262
263 &adm_dma {
264 status = "okay";
265 };
266
267 &mdio0 {
268 status = "okay";
269
270 pinctrl-0 = <&mdio0_pins>;
271 pinctrl-names = "default";
272
273 switch@10 {
274 compatible = "qca,qca8337";
275 #address-cells = <1>;
276 #size-cells = <0>;
277 reg = <0x10>;
278
279 ports {
280 #address-cells = <1>;
281 #size-cells = <0>;
282
283 port@0 {
284 reg = <0>;
285 label = "cpu";
286 ethernet = <&gmac1>;
287 phy-mode = "rgmii";
288 tx-internal-delay-ps = <1000>;
289 rx-internal-delay-ps = <1000>;
290
291 fixed-link {
292 speed = <1000>;
293 full-duplex;
294 };
295 };
296
297 port@1 {
298 reg = <1>;
299 label = "lan1";
300 phy-mode = "internal";
301 phy-handle = <&phy_port1>;
302 };
303
304 port@2 {
305 reg = <2>;
306 label = "lan2";
307 phy-mode = "internal";
308 phy-handle = <&phy_port2>;
309 };
310
311 port@3 {
312 reg = <3>;
313 label = "lan3";
314 phy-mode = "internal";
315 phy-handle = <&phy_port3>;
316 };
317
318 port@4 {
319 reg = <4>;
320 label = "lan4";
321 phy-mode = "internal";
322 phy-handle = <&phy_port4>;
323 };
324
325 port@5 {
326 reg = <5>;
327 label = "wan";
328 phy-mode = "internal";
329 phy-handle = <&phy_port5>;
330 };
331
332 port@6 {
333 reg = <6>;
334 label = "cpu";
335 ethernet = <&gmac2>;
336 phy-mode = "sgmii";
337 qca,sgmii-enable-pll;
338
339 fixed-link {
340 speed = <1000>;
341 full-duplex;
342 };
343 };
344 };
345
346 mdio {
347 #address-cells = <1>;
348 #size-cells = <0>;
349
350 phy_port1: phy@0 {
351 reg = <0>;
352 };
353
354 phy_port2: phy@1 {
355 reg = <1>;
356 };
357
358 phy_port3: phy@2 {
359 reg = <2>;
360 };
361
362 phy_port4: phy@3 {
363 reg = <3>;
364 };
365
366 phy_port5: phy@4 {
367 reg = <4>;
368 };
369 };
370 };
371 };
372
373 &gmac1 {
374 status = "okay";
375
376 pinctrl-0 = <&rgmii2_pins>;
377 pinctrl-names = "default";
378
379 phy-mode = "rgmii";
380 qcom,id = <1>;
381
382 fixed-link {
383 speed = <1000>;
384 full-duplex;
385 };
386 };
387
388 &gmac2 {
389 status = "okay";
390
391 phy-mode = "sgmii";
392 qcom,id = <2>;
393
394 fixed-link {
395 speed = <1000>;
396 full-duplex;
397 };
398 };
399
400 &gsbi4_serial {
401 pinctrl-0 = <&uart0_pins>;
402 pinctrl-names = "default";
403 };
404
405 &flash {
406 compatible = "jedec,spi-nor";
407 };
408
409 &sata_phy {
410 status = "disabled";
411 };
412
413 &sata {
414 status = "disabled";
415 };
416
417 &hs_phy_0 {
418 status = "okay";
419 };
420
421 &ss_phy_0 {
422 status = "okay";
423
424 rx_eq = <2>;
425 tx_deamp_3_5db = <32>;
426 mpll = <160>;
427 };
428
429 &usb3_0 {
430 status = "okay";
431 };
432
433 &hs_phy_1 {
434 status = "okay";
435 };
436
437 &ss_phy_1 {
438 status = "okay";
439
440 rx_eq = <2>;
441 tx_deamp_3_5db = <32>;
442 mpll = <160>;
443 };
444
445 &usb3_1 {
446 status = "okay";
447 };
448
449 &pcie0 {
450 status = "okay";
451
452 /delete-property/ pinctrl-0;
453 /delete-property/ pinctrl-names;
454 /delete-property/ perst-gpios;
455 };
456
457 &pcie1 {
458 status = "okay";
459 };
460
461 &pcie2 {
462 status = "okay";
463
464 /delete-property/ pinctrl-0;
465 /delete-property/ pinctrl-names;
466 /delete-property/ perst-gpios;
467 };
468
469 &qcom_pinmux {
470 pinctrl-names = "default";
471 pinctrl-0 = <&state_default>;
472
473 state_default: pinctrl0 {
474 pcie0_pcie2_perst {
475 pins = "gpio3";
476 function = "gpio";
477 drive-strength = <2>;
478 bias-disable;
479 output-high;
480 };
481 };
482
483 led_pins: led_pins {
484 mux {
485 pins = "gpio7", "gpio8", "gpio9", "gpio22",
486 "gpio23", "gpio24", "gpio25", "gpio53";
487 function = "gpio";
488 drive-strength = <2>;
489 bias-pull-up;
490 };
491 };
492
493 button_pins: button_pins {
494 mux {
495 pins = "gpio54";
496 function = "gpio";
497 drive-strength = <2>;
498 bias-pull-up;
499 };
500 };
501
502 beeper_pins: beeper_pins {
503 mux {
504 pins = "gpio55";
505 function = "gpio";
506 drive-strength = <2>;
507 bias-pull-up;
508 };
509 };
510
511 rpm_pins: rpm_pins {
512 mux {
513 pins = "gpio12", "gpio13";
514 function = "gsbi4";
515 drive-strength = <10>;
516 bias-disable;
517 };
518 };
519
520 uart0_pins: uart0_pins {
521 mux {
522 pins = "gpio10", "gpio11";
523 function = "gsbi4";
524 drive-strength = <10>;
525 bias-disable;
526 };
527 };
528
529 spi_pins: spi_pins {
530 mux {
531 pins = "gpio18", "gpio19";
532 function = "gsbi5";
533 drive-strength = <10>;
534 bias-pull-down;
535 };
536
537 clk {
538 pins = "gpio21";
539 function = "gsbi5";
540 drive-strength = <12>;
541 bias-pull-down;
542 };
543
544 cs {
545 pins = "gpio20";
546 function = "gpio";
547 drive-strength = <10>;
548 bias-pull-up;
549 };
550 };
551 };
552
553 &tcsr {
554 qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
555 };