target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts

   1 #include "qcom-ipq8064-v2.0-smb208.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/leds/common.h>
   5
   6 / {
   7         model = "TP-Link Archer VR2600v";
   8         compatible = "tplink,vr2600v", "qcom,ipq8064";
   9
  10         memory@0 {
  11                 reg = <0x42000000 0x1e000000>;
  12                 device_type = "memory";
  13         };
  14
  15         aliases {
  16                 mdio-gpio0 = &mdio0;
  17
  18                 led-boot = &power;
  19                 led-failsafe = &general;
  20                 led-running = &power;
  21                 led-upgrade = &general;
  22         };
  23
  24         keys {
  25                 compatible = "gpio-keys";
  26                 pinctrl-0 = <&button_pins>;
  27                 pinctrl-names = "default";
  28
  29                 wifi {
  30                         label = "wifi";
  31                         gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  32                         linux,code = <KEY_RFKILL>;
  33                         debounce-interval = <60>;
  34                         wakeup-source;
  35                 };
  36
  37                 reset {
  38                         label = "reset";
  39                         gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
  40                         linux,code = <KEY_RESTART>;
  41                         debounce-interval = <60>;
  42                         wakeup-source;
  43                 };
  44
  45                 wps {
  46                         label = "wps";
  47                         gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  48                         linux,code = <KEY_WPS_BUTTON>;
  49                         debounce-interval = <60>;
  50                         wakeup-source;
  51                 };
  52
  53                 dect {
  54                         label = "dect";
  55                         gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
  56                         linux,code = <KEY_PHONE>;
  57                         debounce-interval = <60>;
  58                         wakeup-source;
  59                 };
  60
  61                 ledswitch {
  62                         label = "ledswitch";
  63                         gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  64                         linux,code = <KEY_LIGHTS_TOGGLE>;
  65                         debounce-interval = <60>;
  66                         wakeup-source;
  67                 };
  68         };
  69
  70         leds {
  71                 compatible = "gpio-leds";
  72                 pinctrl-0 = <&led_pins>;
  73                 pinctrl-names = "default";
  74
  75                 dsl {
  76                         label = "white:dsl";
  77                         gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  78                 };
  79
  80                 usb {
  81                         function = LED_FUNCTION_USB;
  82                         color = <LED_COLOR_ID_WHITE>;
  83                         gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  84                 };
  85
  86                 lan {
  87                         function = LED_FUNCTION_LAN;
  88                         color = <LED_COLOR_ID_WHITE>;
  89                         gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  90                 };
  91
  92                 wlan2g {
  93                         label = "white:wlan2g";
  94                         gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
  95                 };
  96
  97                 wlan5g {
  98                         label = "white:wlan5g";
  99                         gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
 100                 };
 101
 102                 power: power {
 103                         function = LED_FUNCTION_POWER;
 104                         color = <LED_COLOR_ID_WHITE>;
 105                         gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
 106                         default-state = "keep";
 107                 };
 108
 109                 phone {
 110                         label = "white:phone";
 111                         gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
 112                 };
 113
 114                 wan {
 115                         function = LED_FUNCTION_WAN;
 116                         color = <LED_COLOR_ID_WHITE>;
 117                         gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
 118                 };
 119
 120                 general: general {
 121                         label = "white:general";
 122                         gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
 123                 };
 124         };
 125 };
 126
 127 &qcom_pinmux {
 128         led_pins: led_pins {
 129                 mux {
 130                         pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17",
 131                                 "gpio26", "gpio53", "gpio56", "gpio66";
 132                         function = "gpio";
 133                         drive-strength = <2>;
 134                         bias-pull-up;
 135                 };
 136         };
 137
 138         button_pins: button_pins {
 139                 mux {
 140                         pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
 141                         function = "gpio";
 142                         drive-strength = <2>;
 143                         bias-pull-up;
 144                 };
 145         };
 146
 147         spi_pins: spi_pins {
 148                 mux {
 149                         pins = "gpio18", "gpio19", "gpio21";
 150                         function = "gsbi5";
 151                         bias-pull-down;
 152                 };
 153
 154                 data {
 155                         pins = "gpio18", "gpio19";
 156                         drive-strength = <10>;
 157                 };
 158
 159                 cs {
 160                         pins = "gpio20";
 161                         drive-strength = <10>;
 162                         bias-pull-up;
 163                 };
 164
 165                 clk {
 166                         pins = "gpio21";
 167                         drive-strength = <12>;
 168                 };
 169         };
 170 };
 171
 172 &gsbi5 {
 173         qcom,mode = <GSBI_PROT_SPI>;
 174         status = "okay";
 175
 176         spi4: spi@1a280000 {
 177                 status = "okay";
 178
 179                 pinctrl-0 = <&spi_pins>;
 180                 pinctrl-names = "default";
 181
 182                 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
 183
 184                 flash@0 {
 185                         compatible = "jedec,spi-nor";
 186                         #address-cells = <1>;
 187                         #size-cells = <1>;
 188                         spi-max-frequency = <50000000>;
 189                         reg = <0>;
 190
 191                         partitions {
 192                                 compatible = "fixed-partitions";
 193                                 #address-cells = <1>;
 194                                 #size-cells = <1>;
 195
 196                                 partition@0 {
 197                                         label = "SBL1";
 198                                         reg = <0x0 0x20000>;
 199                                         read-only;
 200                                 };
 201
 202                                 partition@20000 {
 203                                         label = "MIBIB";
 204                                         reg = <0x20000 0x20000>;
 205                                         read-only;
 206                                 };
 207
 208                                 partition@40000 {
 209                                         label = "SBL2";
 210                                         reg = <0x40000 0x40000>;
 211                                         read-only;
 212                                 };
 213
 214                                 partition@80000 {
 215                                         label = "SBL3";
 216                                         reg = <0x80000 0x80000>;
 217                                         read-only;
 218                                 };
 219
 220                                 partition@100000 {
 221                                         label = "DDRCONFIG";
 222                                         reg = <0x100000 0x10000>;
 223                                         read-only;
 224                                 };
 225
 226                                 partition@110000 {
 227                                         label = "SSD";
 228                                         reg = <0x110000 0x10000>;
 229                                         read-only;
 230                                 };
 231
 232                                 partition@120000 {
 233                                         label = "TZ";
 234                                         reg = <0x120000 0x80000>;
 235                                         read-only;
 236                                 };
 237
 238                                 partition@1a0000 {
 239                                         label = "RPM";
 240                                         reg = <0x1a0000 0x80000>;
 241                                         read-only;
 242                                 };
 243
 244                                 partition@220000 {
 245                                         label = "APPSBL";
 246                                         reg = <0x220000 0x80000>;
 247                                         read-only;
 248                                 };
 249
 250                                 partition@2a0000 {
 251                                         label = "APPSBLENV";
 252                                         reg = <0x2a0000 0x40000>;
 253                                         read-only;
 254                                 };
 255
 256                                 partition@2e0000 {
 257                                         label = "OLDART";
 258                                         reg = <0x2e0000 0x40000>;
 259                                         read-only;
 260                                 };
 261
 262                                 partition@320000 {
 263                                         label = "firmware";
 264                                         reg = <0x320000 0xc60000>;
 265                                         compatible = "openwrt,uimage";
 266                                         openwrt,offset = <512>; /* account for pad-extra 512 */
 267                                 };
 268
 269                                 /* hole 0xf80000 - 0xfaf100 */
 270
 271                                 partition@faf100 {
 272                                         label = "default-mac";
 273                                         reg = <0xfaf100 0x00200>;
 274                                         read-only;
 275
 276                                         nvmem-layout {
 277                                                 compatible = "fixed-layout";
 278                                                 #address-cells = <1>;
 279                                                 #size-cells = <1>;
 280
 281                                                 macaddr_defaultmac_0: macaddr@0 {
 282                                                         compatible = "mac-base";
 283                                                         reg = <0x0 0x6>;
 284                                                         #nvmem-cell-cells = <1>;
 285                                                 };
 286                                         };
 287                                 };
 288
 289                                 partition@fc0000 {
 290                                         label = "ART";
 291                                         reg = <0xfc0000 0x40000>;
 292                                         read-only;
 293
 294                                         nvmem-layout {
 295                                                 compatible = "fixed-layout";
 296                                                 #address-cells = <1>;
 297                                                 #size-cells = <1>;
 298
 299                                                 precal_ART_1000: precal@1000 {
 300                                                         reg = <0x1000 0x2f20>;
 301                                                 };
 302
 303                                                 precal_ART_5000: precal@5000 {
 304                                                         reg = <0x5000 0x2f20>;
 305                                                 };
 306                                         };
 307                                 };
 308                         };
 309                 };
 310         };
 311 };
 312
 313 &hs_phy_0 {
 314         status = "okay";
 315 };
 316
 317 &ss_phy_0 {
 318         status = "okay";
 319 };
 320
 321 &usb3_0 {
 322         status = "okay";
 323 };
 324
 325 &hs_phy_1 {
 326         status = "okay";
 327 };
 328
 329 &ss_phy_1 {
 330         status = "okay";
 331 };
 332
 333 &usb3_1 {
 334         status = "okay";
 335 };
 336
 337 &pcie0 {
 338         status = "okay";
 339
 340         bridge@0,0 {
 341                 reg = <0x00000000 0 0 0 0>;
 342                 #address-cells = <3>;
 343                 #size-cells = <2>;
 344                 ranges;
 345
 346                 wifi@1,0 {
 347                         compatible = "pci168c,0040";
 348                         reg = <0x00010000 0 0 0 0>;
 349
 350                         nvmem-cells = <&macaddr_defaultmac_0 (-1)>, <&precal_ART_1000>;
 351                         nvmem-cell-names = "mac-address", "pre-calibration";
 352                 };
 353         };
 354 };
 355
 356 &pcie1 {
 357         status = "okay";
 358         max-link-speed = <1>;
 359
 360         bridge@0,0 {
 361                 reg = <0x00000000 0 0 0 0>;
 362                 #address-cells = <3>;
 363                 #size-cells = <2>;
 364                 ranges;
 365
 366                 wifi@1,0 {
 367                         compatible = "pci168c,0040";
 368                         reg = <0x00010000 0 0 0 0>;
 369
 370                         nvmem-cells = <&macaddr_defaultmac_0 0>, <&precal_ART_5000>;
 371                         nvmem-cell-names = "mac-address", "pre-calibration";
 372                 };
 373         };
 374 };
 375
 376 &mdio0 {
 377         status = "okay";
 378
 379         pinctrl-0 = <&mdio0_pins>;
 380         pinctrl-names = "default";
 381
 382         switch@10 {
 383                 compatible = "qca,qca8337";
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 reg = <0x10>;
 387
 388                 ports {
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391
 392                         port@0 {
 393                                 reg = <0>;
 394                                 label = "cpu";
 395                                 ethernet = <&gmac1>;
 396                                 phy-mode = "rgmii";
 397                                 tx-internal-delay-ps = <1000>;
 398                                 rx-internal-delay-ps = <1000>;
 399
 400                                 fixed-link {
 401                                         speed = <1000>;
 402                                         full-duplex;
 403                                 };
 404                         };
 405
 406                         port@1 {
 407                                 reg = <1>;
 408                                 label = "lan4";
 409                                 phy-mode = "internal";
 410                                 phy-handle = <&phy_port1>;
 411                         };
 412
 413                         port@2 {
 414                                 reg = <2>;
 415                                 label = "lan3";
 416                                 phy-mode = "internal";
 417                                 phy-handle = <&phy_port2>;
 418                         };
 419
 420                         port@3 {
 421                                 reg = <3>;
 422                                 label = "lan2";
 423                                 phy-mode = "internal";
 424                                 phy-handle = <&phy_port3>;
 425                         };
 426
 427                         port@4 {
 428                                 reg = <4>;
 429                                 label = "lan1";
 430                                 phy-mode = "internal";
 431                                 phy-handle = <&phy_port4>;
 432                         };
 433
 434                         port@5 {
 435                                 reg = <5>;
 436                                 label = "wan";
 437                                 phy-mode = "internal";
 438                                 phy-handle = <&phy_port5>;
 439                         };
 440
 441                         port@6 {
 442                                 reg = <6>;
 443                                 label = "cpu";
 444                                 ethernet = <&gmac2>;
 445                                 phy-mode = "sgmii";
 446                                 qca,sgmii-enable-pll;
 447
 448                                 fixed-link {
 449                                         speed = <1000>;
 450                                         full-duplex;
 451                                 };
 452                         };
 453                 };
 454
 455                 mdio {
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458
 459                         phy_port1: phy@0 {
 460                                 reg = <0>;
 461                         };
 462
 463                         phy_port2: phy@1 {
 464                                 reg = <1>;
 465                         };
 466
 467                         phy_port3: phy@2 {
 468                                 reg = <2>;
 469                         };
 470
 471                         phy_port4: phy@3 {
 472                                 reg = <3>;
 473                         };
 474
 475                         phy_port5: phy@4 {
 476                                 reg = <4>;
 477                         };
 478                 };
 479         };
 480 };
 481
 482 &gmac1 {
 483         status = "okay";
 484         phy-mode = "rgmii";
 485         qcom,id = <1>;
 486
 487         pinctrl-0 = <&rgmii2_pins>;
 488         pinctrl-names = "default";
 489
 490         nvmem-cells = <&macaddr_defaultmac_0 1>;
 491         nvmem-cell-names = "mac-address";
 492
 493         fixed-link {
 494                 speed = <1000>;
 495                 full-duplex;
 496         };
 497 };
 498
 499 &gmac2 {
 500         status = "okay";
 501         phy-mode = "sgmii";
 502         qcom,id = <2>;
 503
 504         nvmem-cells = <&macaddr_defaultmac_0 0>;
 505         nvmem-cell-names = "mac-address";
 506
 507         fixed-link {
 508                 speed = <1000>;
 509                 full-duplex;
 510         };
 511 };
 512
 513 &adm_dma {
 514         status = "okay";
 515 };