target/linux/ipq40xx/patches-6.1/705-ARM-dts-qcom-ipq4019-Add-description-for-the-IPQESS-.patch

   1 From 5b71dbb867680887d47954ce1cc145cb747cbce6 Mon Sep 17 00:00:00 2001
   2 From: Maxime Chevallier <maxime.chevallier@bootlin.com>
   3 Date: Fri, 4 Nov 2022 18:41:51 +0100
   4 Subject: [PATCH] ARM: dts: qcom: ipq4019: Add description for the IPQESS
   5  Ethernet controller
   6
   7 The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
   8 connected to the CPU through the internal IPQESS Ethernet controller.
   9
  10 Add support for this internal interface, which is internally connected to a
  11 modified version of the QCA8K Ethernet switch.
  12
  13 This Ethernet controller only support a specific internal interface mode
  14 for connection to the switch.
  15
  16 Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
  17 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  18 ---
  19  arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
  20  1 file changed, 48 insertions(+)
  21
  22 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  23 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  24 @@ -591,6 +591,54 @@
  25                         status = "disabled";
  26                 };
  27
  28 +               gmac: ethernet@c080000 {
  29 +                       compatible = "qcom,ipq4019-ess-edma";
  30 +                       reg = <0xc080000 0x8000>;
  31 +                       resets = <&gcc ESS_RESET>;
  32 +                       reset-names = "ess";
  33 +                       clocks = <&gcc GCC_ESS_CLK>;
  34 +                       clock-names = "ess";
  35 +                       interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
  36 +                                    <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
  37 +                                    <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
  38 +                                    <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
  39 +                                    <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
  40 +                                    <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
  41 +                                    <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
  42 +                                    <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
  43 +                                    <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
  44 +                                    <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
  45 +                                    <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
  46 +                                    <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
  47 +                                    <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
  48 +                                    <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
  49 +                                    <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
  50 +                                    <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
  51 +                                    <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
  52 +                                    <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
  53 +                                    <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
  54 +                                    <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
  55 +                                    <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
  56 +                                    <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
  57 +                                    <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
  58 +                                    <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
  59 +                                    <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
  60 +                                    <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
  61 +                                    <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
  62 +                                    <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
  63 +                                    <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
  64 +                                    <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
  65 +                                    <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
  66 +                                    <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
  67 +                       phy-mode = "internal";
  68 +                       status = "disabled";
  69 +                       fixed-link {
  70 +                               speed = <1000>;
  71 +                               full-duplex;
  72 +                               pause;
  73 +                       };
  74 +               };
  75 +
  76                 mdio: mdio@90000 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;