target/linux/imx/patches-6.1/001-6.2-phy-freescale-imx8m-pcie-Refine-register-definitions.patch

   1 From ffcbb4ccd357eeb649036e379a34bf5fb8d4f47c Mon Sep 17 00:00:00 2001
   2 From: Richard Zhu <hongxing.zhu@nxp.com>
   3 Date: Thu, 13 Oct 2022 09:47:00 +0800
   4 Subject: [PATCH 1/3] phy: freescale: imx8m-pcie: Refine register definitions
   5
   6 No function changes, refine PHY register definitions.
   7 - Keep align with other CMN PHY registers, refine the definitions of
   8   PHY_CMN_REG75.
   9 - Remove two BIT definitions that are not used at all.
  10
  11 Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
  12 Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
  13 Tested-by: Marek Vasut <marex@denx.de>
  14 Tested-by: Richard Leitner <richard.leitner@skidata.com>
  15 Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
  16 Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  17 ---
  18  drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 11 ++++-------
  19  1 file changed, 4 insertions(+), 7 deletions(-)
  20
  21 --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
  22 +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
  23 @@ -31,12 +31,10 @@
  24  #define IMX8MM_PCIE_PHY_CMN_REG065     0x194
  25  #define  ANA_AUX_RX_TERM               (BIT(7) | BIT(4))
  26  #define  ANA_AUX_TX_LVL                        GENMASK(3, 0)
  27 -#define IMX8MM_PCIE_PHY_CMN_REG75      0x1D4
  28 -#define  PCIE_PHY_CMN_REG75_PLL_DONE   0x3
  29 +#define IMX8MM_PCIE_PHY_CMN_REG075     0x1D4
  30 +#define  ANA_PLL_DONE                  0x3
  31  #define PCIE_PHY_TRSV_REG5             0x414
  32 -#define  PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
  33  #define PCIE_PHY_TRSV_REG6             0x418
  34 -#define  PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
  35
  36  #define IMX8MM_GPR_PCIE_REF_CLK_SEL    GENMASK(25, 24)
  37  #define IMX8MM_GPR_PCIE_REF_CLK_PLL    FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
  38 @@ -131,9 +129,8 @@ static int imx8_pcie_phy_power_on(struct
  39         reset_control_deassert(imx8_phy->reset);
  40
  41         /* Polling to check the phy is ready or not. */
  42 -       ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
  43 -                                val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
  44 -                                10, 20000);
  45 +       ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
  46 +                                val, val == ANA_PLL_DONE, 10, 20000);
  47         return ret;
  48  }
  49