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perf: fix build on PowerPC
[openwrt/staging/stintel.git] / target / linux / generic / pending-6.6 / 745-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch
1 From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
3 Date: Mon, 22 Apr 2024 10:15:09 +0300
4 Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P()
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
10 MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
11 for MT7530 only. Add MT7530 prefix to the definition for bit 15.
12
13 Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
14
15 Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
16 follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
17 "MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
18 Generation Router Platform: Datasheet (Open Version) v0.1" documents.
19
20 These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
21 with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
22
23 Remove PMCR_SPEED_MASK which doesn't have a use.
24
25 Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
26 end for the mask that includes all force mode definitions.
27
28 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
29 ---
30 drivers/net/dsa/mt7530.c | 24 ++++++++---------
31 drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++-------------------
32 2 files changed, 42 insertions(+), 40 deletions(-)
33
34 --- a/drivers/net/dsa/mt7530.c
35 +++ b/drivers/net/dsa/mt7530.c
36 @@ -896,7 +896,7 @@ static void mt7530_setup_port5(struct ds
37 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
38
39 /* Setup the MAC by default for the cpu port */
40 - mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
41 + mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
42 break;
43 case P5_INTF_SEL_GMAC5:
44 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
45 @@ -2444,8 +2444,8 @@ mt7530_setup(struct dsa_switch *ds)
46 /* Clear link settings and enable force mode to force link down
47 * on all ports until they're enabled later.
48 */
49 - mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
50 - PMCR_FORCE_MODE, PMCR_FORCE_MODE);
51 + mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
52 + MT7530_FORCE_MODE, MT7530_FORCE_MODE);
53
54 /* Disable forwarding by default on all ports */
55 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
56 @@ -2555,8 +2555,8 @@ mt7531_setup_common(struct dsa_switch *d
57 /* Clear link settings and enable force mode to force link down
58 * on all ports until they're enabled later.
59 */
60 - mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
61 - MT7531_FORCE_MODE, MT7531_FORCE_MODE);
62 + mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
63 + MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
64
65 /* Disable forwarding by default on all ports */
66 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
67 @@ -2639,7 +2639,7 @@ mt7531_setup(struct dsa_switch *ds)
68
69 /* Force link down on all ports before internal reset */
70 for (i = 0; i < MT7530_NUM_PORTS; i++)
71 - mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
72 + mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
73
74 /* Reset the switch through internal reset */
75 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
76 @@ -2881,7 +2881,7 @@ mt753x_phylink_mac_config(struct phylink
77
78 /* Are we connected to external phy */
79 if (port == 5 && dsa_is_user_port(ds, 5))
80 - mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
81 + mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
82 }
83
84 static void mt753x_phylink_mac_link_down(struct phylink_config *config,
85 @@ -2891,7 +2891,7 @@ static void mt753x_phylink_mac_link_down
86 struct dsa_port *dp = dsa_phylink_to_port(config);
87 struct mt7530_priv *priv = dp->ds->priv;
88
89 - mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
90 + mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
91 }
92
93 static void mt753x_phylink_mac_link_up(struct phylink_config *config,
94 @@ -2905,7 +2905,7 @@ static void mt753x_phylink_mac_link_up(s
95 struct mt7530_priv *priv = dp->ds->priv;
96 u32 mcr;
97
98 - mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
99 + mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK;
100
101 switch (speed) {
102 case SPEED_1000:
103 @@ -2920,9 +2920,9 @@ static void mt753x_phylink_mac_link_up(s
104 if (duplex == DUPLEX_FULL) {
105 mcr |= PMCR_FORCE_FDX;
106 if (tx_pause)
107 - mcr |= PMCR_TX_FC_EN;
108 + mcr |= PMCR_FORCE_TX_FC_EN;
109 if (rx_pause)
110 - mcr |= PMCR_RX_FC_EN;
111 + mcr |= PMCR_FORCE_RX_FC_EN;
112 }
113
114 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
115 @@ -2937,7 +2937,7 @@ static void mt753x_phylink_mac_link_up(s
116 }
117 }
118
119 - mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
120 + mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
121 }
122
123 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
124 --- a/drivers/net/dsa/mt7530.h
125 +++ b/drivers/net/dsa/mt7530.h
126 @@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm {
127 #define G0_PORT_VID_DEF G0_PORT_VID(0)
128
129 /* Register for port MAC control register */
130 -#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
131 -#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
132 +#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
133 +#define PMCR_IFG_XMIT_MASK GENMASK(19, 18)
134 +#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
135 #define PMCR_EXT_PHY BIT(17)
136 #define PMCR_MAC_MODE BIT(16)
137 -#define PMCR_FORCE_MODE BIT(15)
138 -#define PMCR_TX_EN BIT(14)
139 -#define PMCR_RX_EN BIT(13)
140 +#define MT7530_FORCE_MODE BIT(15)
141 +#define PMCR_MAC_TX_EN BIT(14)
142 +#define PMCR_MAC_RX_EN BIT(13)
143 #define PMCR_BACKOFF_EN BIT(9)
144 #define PMCR_BACKPR_EN BIT(8)
145 #define PMCR_FORCE_EEE1G BIT(7)
146 #define PMCR_FORCE_EEE100 BIT(6)
147 -#define PMCR_TX_FC_EN BIT(5)
148 -#define PMCR_RX_FC_EN BIT(4)
149 +#define PMCR_FORCE_RX_FC_EN BIT(5)
150 +#define PMCR_FORCE_TX_FC_EN BIT(4)
151 #define PMCR_FORCE_SPEED_1000 BIT(3)
152 #define PMCR_FORCE_SPEED_100 BIT(2)
153 #define PMCR_FORCE_FDX BIT(1)
154 #define PMCR_FORCE_LNK BIT(0)
155 -#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
156 - PMCR_FORCE_SPEED_1000)
157 -#define MT7531_FORCE_LNK BIT(31)
158 -#define MT7531_FORCE_SPD BIT(30)
159 -#define MT7531_FORCE_DPX BIT(29)
160 -#define MT7531_FORCE_RX_FC BIT(28)
161 -#define MT7531_FORCE_TX_FC BIT(27)
162 -#define MT7531_FORCE_EEE100 BIT(26)
163 -#define MT7531_FORCE_EEE1G BIT(25)
164 -#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
165 - MT7531_FORCE_SPD | \
166 - MT7531_FORCE_DPX | \
167 - MT7531_FORCE_RX_FC | \
168 - MT7531_FORCE_TX_FC | \
169 - MT7531_FORCE_EEE100 | \
170 - MT7531_FORCE_EEE1G)
171 -#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
172 - PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
173 - PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
174 - PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
175 - PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
176 +#define MT7531_FORCE_MODE_LNK BIT(31)
177 +#define MT7531_FORCE_MODE_SPD BIT(30)
178 +#define MT7531_FORCE_MODE_DPX BIT(29)
179 +#define MT7531_FORCE_MODE_RX_FC BIT(28)
180 +#define MT7531_FORCE_MODE_TX_FC BIT(27)
181 +#define MT7531_FORCE_MODE_EEE100 BIT(26)
182 +#define MT7531_FORCE_MODE_EEE1G BIT(25)
183 +#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \
184 + MT7531_FORCE_MODE_SPD | \
185 + MT7531_FORCE_MODE_DPX | \
186 + MT7531_FORCE_MODE_RX_FC | \
187 + MT7531_FORCE_MODE_TX_FC | \
188 + MT7531_FORCE_MODE_EEE100 | \
189 + MT7531_FORCE_MODE_EEE1G)
190 +#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
191 + PMCR_FORCE_EEE1G | \
192 + PMCR_FORCE_EEE100 | \
193 + PMCR_FORCE_RX_FC_EN | \
194 + PMCR_FORCE_TX_FC_EN | \
195 + PMCR_FORCE_SPEED_1000 | \
196 + PMCR_FORCE_SPEED_100 | \
197 + PMCR_FORCE_FDX | PMCR_FORCE_LNK)
198
199 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
200 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
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