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perf: fix build on PowerPC
[openwrt/staging/stintel.git] / target / linux / generic / backport-6.6 / 752-14-v6.7-net-ethernet-mtk_wed-introduce-WED-support-for-MT798.patch
1 From: Sujuan Chen <sujuan.chen@mediatek.com>
2 Date: Mon, 18 Sep 2023 12:29:13 +0200
3 Subject: [PATCH] net: ethernet: mtk_wed: introduce WED support for MT7988
4
5 Similar to MT7986 and MT7622, enable Wireless Ethernet Ditpatcher for
6 MT7988 in order to offload traffic forwarded from LAN/WLAN to WLAN/LAN
7
8 Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
9 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
10 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
11 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
12 ---
13
14 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
15 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
16 @@ -197,6 +197,7 @@ static const struct mtk_reg_map mt7988_r
17 .wdma_base = {
18 [0] = 0x4800,
19 [1] = 0x4c00,
20 + [2] = 0x5000,
21 },
22 .pse_iq_sta = 0x0180,
23 .pse_oq_sta = 0x01a0,
24 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
25 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
26 @@ -1132,7 +1132,7 @@ struct mtk_reg_map {
27 u32 gdm1_cnt;
28 u32 gdma_to_ppe;
29 u32 ppe_base;
30 - u32 wdma_base[2];
31 + u32 wdma_base[3];
32 u32 pse_iq_sta;
33 u32 pse_oq_sta;
34 };
35 --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
36 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
37 @@ -201,6 +201,9 @@ mtk_flow_set_output_device(struct mtk_et
38 case 1:
39 pse_port = PSE_WDMA1_PORT;
40 break;
41 + case 2:
42 + pse_port = PSE_WDMA2_PORT;
43 + break;
44 default:
45 return -EINVAL;
46 }
47 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
48 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
49 @@ -17,17 +17,19 @@
50 #include <net/flow_offload.h>
51 #include <net/pkt_cls.h>
52 #include "mtk_eth_soc.h"
53 -#include "mtk_wed_regs.h"
54 #include "mtk_wed.h"
55 #include "mtk_ppe.h"
56 #include "mtk_wed_wo.h"
57
58 #define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
59
60 -#define MTK_WED_PKT_SIZE 1900
61 +#define MTK_WED_PKT_SIZE 1920
62 #define MTK_WED_BUF_SIZE 2048
63 +#define MTK_WED_PAGE_BUF_SIZE 128
64 #define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048)
65 +#define MTK_WED_RX_PAGE_BUF_PER_PAGE (PAGE_SIZE / 128)
66 #define MTK_WED_RX_RING_SIZE 1536
67 +#define MTK_WED_RX_PG_BM_CNT 8192
68
69 #define MTK_WED_TX_RING_SIZE 2048
70 #define MTK_WED_WDMA_RING_SIZE 1024
71 @@ -41,7 +43,10 @@
72 #define MTK_WED_RRO_QUE_CNT 8192
73 #define MTK_WED_MIOD_ENTRY_CNT 128
74
75 -static struct mtk_wed_hw *hw_list[2];
76 +#define MTK_WED_TX_BM_DMA_SIZE 65536
77 +#define MTK_WED_TX_BM_PKT_CNT 32768
78 +
79 +static struct mtk_wed_hw *hw_list[3];
80 static DEFINE_MUTEX(hw_lock);
81
82 struct mtk_wed_flow_block_priv {
83 @@ -56,6 +61,7 @@ static const struct mtk_wed_soc_data mt7
84 .reset_idx_tx_mask = GENMASK(3, 0),
85 .reset_idx_rx_mask = GENMASK(17, 16),
86 },
87 + .tx_ring_desc_size = sizeof(struct mtk_wdma_desc),
88 .wdma_desc_size = sizeof(struct mtk_wdma_desc),
89 };
90
91 @@ -66,6 +72,18 @@ static const struct mtk_wed_soc_data mt7
92 .reset_idx_tx_mask = GENMASK(1, 0),
93 .reset_idx_rx_mask = GENMASK(7, 6),
94 },
95 + .tx_ring_desc_size = sizeof(struct mtk_wdma_desc),
96 + .wdma_desc_size = 2 * sizeof(struct mtk_wdma_desc),
97 +};
98 +
99 +static const struct mtk_wed_soc_data mt7988_data = {
100 + .regmap = {
101 + .tx_bm_tkid = 0x0c8,
102 + .wpdma_rx_ring0 = 0x7d0,
103 + .reset_idx_tx_mask = GENMASK(1, 0),
104 + .reset_idx_rx_mask = GENMASK(7, 6),
105 + },
106 + .tx_ring_desc_size = sizeof(struct mtk_wed_bm_desc),
107 .wdma_desc_size = 2 * sizeof(struct mtk_wdma_desc),
108 };
109
110 @@ -320,33 +338,38 @@ out:
111 static int
112 mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
113 {
114 + u32 desc_size = dev->hw->soc->tx_ring_desc_size;
115 + int i, page_idx = 0, n_pages, ring_size;
116 + int token = dev->wlan.token_start;
117 struct mtk_wed_buf *page_list;
118 - struct mtk_wdma_desc *desc;
119 dma_addr_t desc_phys;
120 - int token = dev->wlan.token_start;
121 - int ring_size;
122 - int n_pages;
123 - int i, page_idx;
124 + void *desc_ptr;
125
126 - ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
127 - n_pages = ring_size / MTK_WED_BUF_PER_PAGE;
128 + if (!mtk_wed_is_v3_or_greater(dev->hw)) {
129 + ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
130 + dev->tx_buf_ring.size = ring_size;
131 + } else {
132 + dev->tx_buf_ring.size = MTK_WED_TX_BM_DMA_SIZE;
133 + ring_size = MTK_WED_TX_BM_PKT_CNT;
134 + }
135 + n_pages = dev->tx_buf_ring.size / MTK_WED_BUF_PER_PAGE;
136
137 page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
138 if (!page_list)
139 return -ENOMEM;
140
141 - dev->tx_buf_ring.size = ring_size;
142 dev->tx_buf_ring.pages = page_list;
143
144 - desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
145 - &desc_phys, GFP_KERNEL);
146 - if (!desc)
147 + desc_ptr = dma_alloc_coherent(dev->hw->dev,
148 + dev->tx_buf_ring.size * desc_size,
149 + &desc_phys, GFP_KERNEL);
150 + if (!desc_ptr)
151 return -ENOMEM;
152
153 - dev->tx_buf_ring.desc = desc;
154 + dev->tx_buf_ring.desc = desc_ptr;
155 dev->tx_buf_ring.desc_phys = desc_phys;
156
157 - for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
158 + for (i = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
159 dma_addr_t page_phys, buf_phys;
160 struct page *page;
161 void *buf;
162 @@ -372,28 +395,31 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
163 buf_phys = page_phys;
164
165 for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
166 - u32 txd_size;
167 - u32 ctrl;
168 -
169 - txd_size = dev->wlan.init_buf(buf, buf_phys, token++);
170 + struct mtk_wdma_desc *desc = desc_ptr;
171
172 desc->buf0 = cpu_to_le32(buf_phys);
173 - desc->buf1 = cpu_to_le32(buf_phys + txd_size);
174 + if (!mtk_wed_is_v3_or_greater(dev->hw)) {
175 + u32 txd_size, ctrl;
176
177 - if (mtk_wed_is_v1(dev->hw))
178 - ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) |
179 - FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
180 - MTK_WED_BUF_SIZE - txd_size) |
181 - MTK_WDMA_DESC_CTRL_LAST_SEG1;
182 - else
183 - ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) |
184 - FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
185 - MTK_WED_BUF_SIZE - txd_size) |
186 - MTK_WDMA_DESC_CTRL_LAST_SEG0;
187 - desc->ctrl = cpu_to_le32(ctrl);
188 - desc->info = 0;
189 - desc++;
190 + txd_size = dev->wlan.init_buf(buf, buf_phys,
191 + token++);
192 + desc->buf1 = cpu_to_le32(buf_phys + txd_size);
193 + ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size);
194 + if (mtk_wed_is_v1(dev->hw))
195 + ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG1 |
196 + FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
197 + MTK_WED_BUF_SIZE - txd_size);
198 + else
199 + ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG0 |
200 + FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
201 + MTK_WED_BUF_SIZE - txd_size);
202 + desc->ctrl = cpu_to_le32(ctrl);
203 + desc->info = 0;
204 + } else {
205 + desc->ctrl = cpu_to_le32(token << 16);
206 + }
207
208 + desc_ptr += desc_size;
209 buf += MTK_WED_BUF_SIZE;
210 buf_phys += MTK_WED_BUF_SIZE;
211 }
212 @@ -409,31 +435,31 @@ static void
213 mtk_wed_free_tx_buffer(struct mtk_wed_device *dev)
214 {
215 struct mtk_wed_buf *page_list = dev->tx_buf_ring.pages;
216 - struct mtk_wdma_desc *desc = dev->tx_buf_ring.desc;
217 - int page_idx;
218 - int i;
219 + struct mtk_wed_hw *hw = dev->hw;
220 + int i, page_idx = 0;
221
222 if (!page_list)
223 return;
224
225 - if (!desc)
226 + if (!dev->tx_buf_ring.desc)
227 goto free_pagelist;
228
229 - for (i = 0, page_idx = 0; i < dev->tx_buf_ring.size;
230 - i += MTK_WED_BUF_PER_PAGE) {
231 - dma_addr_t buf_addr = page_list[page_idx].phy_addr;
232 + for (i = 0; i < dev->tx_buf_ring.size; i += MTK_WED_BUF_PER_PAGE) {
233 + dma_addr_t page_phy = page_list[page_idx].phy_addr;
234 void *page = page_list[page_idx++].p;
235
236 if (!page)
237 break;
238
239 - dma_unmap_page(dev->hw->dev, buf_addr, PAGE_SIZE,
240 + dma_unmap_page(dev->hw->dev, page_phy, PAGE_SIZE,
241 DMA_BIDIRECTIONAL);
242 __free_page(page);
243 }
244
245 - dma_free_coherent(dev->hw->dev, dev->tx_buf_ring.size * sizeof(*desc),
246 - desc, dev->tx_buf_ring.desc_phys);
247 + dma_free_coherent(dev->hw->dev,
248 + dev->tx_buf_ring.size * hw->soc->tx_ring_desc_size,
249 + dev->tx_buf_ring.desc,
250 + dev->tx_buf_ring.desc_phys);
251
252 free_pagelist:
253 kfree(page_list);
254 @@ -518,13 +544,23 @@ mtk_wed_set_ext_int(struct mtk_wed_devic
255 {
256 u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
257
258 - if (mtk_wed_is_v1(dev->hw))
259 + switch (dev->hw->version) {
260 + case 1:
261 mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
262 - else
263 + break;
264 + case 2:
265 mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
266 MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH |
267 MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
268 MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR;
269 + break;
270 + case 3:
271 + mask = MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
272 + MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
273 + break;
274 + default:
275 + break;
276 + }
277
278 if (!dev->hw->num_flows)
279 mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
280 @@ -536,6 +572,9 @@ mtk_wed_set_ext_int(struct mtk_wed_devic
281 static void
282 mtk_wed_set_512_support(struct mtk_wed_device *dev, bool enable)
283 {
284 + if (!mtk_wed_is_v2(dev->hw))
285 + return;
286 +
287 if (enable) {
288 wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
289 wed_w32(dev, MTK_WED_TXP_DW1,
290 @@ -610,6 +649,14 @@ mtk_wed_dma_disable(struct mtk_wed_devic
291 MTK_WED_WPDMA_RX_D_RX_DRV_EN);
292 wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
293 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
294 +
295 + if (mtk_wed_is_v3_or_greater(dev->hw) &&
296 + mtk_wed_get_rx_capa(dev)) {
297 + wdma_clr(dev, MTK_WDMA_PREF_TX_CFG,
298 + MTK_WDMA_PREF_TX_CFG_PREF_EN);
299 + wdma_clr(dev, MTK_WDMA_PREF_RX_CFG,
300 + MTK_WDMA_PREF_RX_CFG_PREF_EN);
301 + }
302 }
303
304 mtk_wed_set_512_support(dev, false);
305 @@ -652,6 +699,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
306 MTK_WED_CTRL_RX_ROUTE_QM_EN |
307 MTK_WED_CTRL_WED_RX_BM_EN |
308 MTK_WED_CTRL_RX_RRO_QM_EN);
309 +
310 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
311 + wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
312 + wed_clr(dev, MTK_WED_RESET, MTK_WED_RESET_TX_AMSDU);
313 + wed_clr(dev, MTK_WED_PCIE_INT_CTRL,
314 + MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
315 + MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER);
316 + }
317 }
318
319 static void
320 @@ -701,21 +756,37 @@ mtk_wed_detach(struct mtk_wed_device *de
321 mutex_unlock(&hw_lock);
322 }
323
324 -#define PCIE_BASE_ADDR0 0x11280000
325 static void
326 mtk_wed_bus_init(struct mtk_wed_device *dev)
327 {
328 switch (dev->wlan.bus_type) {
329 case MTK_WED_BUS_PCIE: {
330 struct device_node *np = dev->hw->eth->dev->of_node;
331 - struct regmap *regs;
332
333 - regs = syscon_regmap_lookup_by_phandle(np,
334 - "mediatek,wed-pcie");
335 - if (IS_ERR(regs))
336 - break;
337 + if (mtk_wed_is_v2(dev->hw)) {
338 + struct regmap *regs;
339 +
340 + regs = syscon_regmap_lookup_by_phandle(np,
341 + "mediatek,wed-pcie");
342 + if (IS_ERR(regs))
343 + break;
344
345 - regmap_update_bits(regs, 0, BIT(0), BIT(0));
346 + regmap_update_bits(regs, 0, BIT(0), BIT(0));
347 + }
348 +
349 + if (dev->wlan.msi) {
350 + wed_w32(dev, MTK_WED_PCIE_CFG_INTM,
351 + dev->hw->pcie_base | 0xc08);
352 + wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
353 + dev->hw->pcie_base | 0xc04);
354 + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(8));
355 + } else {
356 + wed_w32(dev, MTK_WED_PCIE_CFG_INTM,
357 + dev->hw->pcie_base | 0x180);
358 + wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
359 + dev->hw->pcie_base | 0x184);
360 + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
361 + }
362
363 wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
364 FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
365 @@ -723,19 +794,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
366 /* pcie interrupt control: pola/source selection */
367 wed_set(dev, MTK_WED_PCIE_INT_CTRL,
368 MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
369 - FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1));
370 - wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
371 -
372 - wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180);
373 - wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184);
374 -
375 - /* pcie interrupt status trigger register */
376 - wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
377 - wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER);
378 -
379 - /* pola setting */
380 - wed_set(dev, MTK_WED_PCIE_INT_CTRL,
381 - MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA);
382 + MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER |
383 + FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL,
384 + dev->hw->index));
385 break;
386 }
387 case MTK_WED_BUS_AXI:
388 @@ -773,18 +834,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
389 static void
390 mtk_wed_hw_init_early(struct mtk_wed_device *dev)
391 {
392 - u32 mask, set;
393 + u32 set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2);
394 + u32 mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE;
395
396 mtk_wed_deinit(dev);
397 mtk_wed_reset(dev, MTK_WED_RESET_WED);
398 mtk_wed_set_wpdma(dev);
399
400 - mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
401 - MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
402 - MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
403 - set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |
404 - MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
405 - MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
406 + if (!mtk_wed_is_v3_or_greater(dev->hw)) {
407 + mask |= MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
408 + MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
409 + set |= MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
410 + MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
411 + }
412 wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
413
414 if (mtk_wed_is_v1(dev->hw)) {
415 @@ -932,11 +994,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
416 }
417
418 /* configure RX_ROUTE_QM */
419 - wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
420 - wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
421 - wed_set(dev, MTK_WED_RTQM_GLO_CFG,
422 - FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT, 0x3 + dev->hw->index));
423 - wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
424 + if (mtk_wed_is_v2(dev->hw)) {
425 + wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
426 + wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
427 + wed_set(dev, MTK_WED_RTQM_GLO_CFG,
428 + FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT,
429 + 0x3 + dev->hw->index));
430 + wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
431 + } else {
432 + wed_set(dev, MTK_WED_RTQM_ENQ_CFG0,
433 + FIELD_PREP(MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT,
434 + 0x3 + dev->hw->index));
435 + }
436 /* enable RX_ROUTE_QM */
437 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
438 }
439 @@ -949,22 +1018,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
440
441 dev->init_done = true;
442 mtk_wed_set_ext_int(dev, false);
443 - wed_w32(dev, MTK_WED_TX_BM_CTRL,
444 - MTK_WED_TX_BM_CTRL_PAUSE |
445 - FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
446 - dev->tx_buf_ring.size / 128) |
447 - FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
448 - MTK_WED_TX_RING_SIZE / 256));
449
450 wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys);
451 -
452 wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
453
454 if (mtk_wed_is_v1(dev->hw)) {
455 + wed_w32(dev, MTK_WED_TX_BM_CTRL,
456 + MTK_WED_TX_BM_CTRL_PAUSE |
457 + FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
458 + dev->tx_buf_ring.size / 128) |
459 + FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
460 + MTK_WED_TX_RING_SIZE / 256));
461 wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
462 FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |
463 MTK_WED_TX_BM_DYN_THR_HI);
464 - } else {
465 + } else if (mtk_wed_is_v2(dev->hw)) {
466 + wed_w32(dev, MTK_WED_TX_BM_CTRL,
467 + MTK_WED_TX_BM_CTRL_PAUSE |
468 + FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
469 + dev->tx_buf_ring.size / 128) |
470 + FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
471 + MTK_WED_TX_RING_SIZE / 256));
472 + wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
473 + FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
474 + MTK_WED_TX_TKID_DYN_THR_HI);
475 wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
476 FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
477 MTK_WED_TX_BM_DYN_THR_HI_V2);
478 @@ -974,9 +1051,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
479 dev->tx_buf_ring.size / 128) |
480 FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
481 dev->tx_buf_ring.size / 128));
482 - wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
483 - FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
484 - MTK_WED_TX_TKID_DYN_THR_HI);
485 }
486
487 wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid,
488 @@ -986,26 +1060,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
489
490 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
491
492 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
493 + /* switch to new bm architecture */
494 + wed_clr(dev, MTK_WED_TX_BM_CTRL,
495 + MTK_WED_TX_BM_CTRL_LEGACY_EN);
496 +
497 + wed_w32(dev, MTK_WED_TX_TKID_CTRL,
498 + MTK_WED_TX_TKID_CTRL_PAUSE |
499 + FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3,
500 + dev->wlan.nbuf / 128) |
501 + FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3,
502 + dev->wlan.nbuf / 128));
503 + /* return SKBID + SDP back to bm */
504 + wed_set(dev, MTK_WED_TX_TKID_CTRL,
505 + MTK_WED_TX_TKID_CTRL_FREE_FORMAT);
506 +
507 + wed_w32(dev, MTK_WED_TX_BM_INIT_PTR,
508 + MTK_WED_TX_BM_PKT_CNT |
509 + MTK_WED_TX_BM_INIT_SW_TAIL_IDX);
510 + }
511 +
512 if (mtk_wed_is_v1(dev->hw)) {
513 wed_set(dev, MTK_WED_CTRL,
514 MTK_WED_CTRL_WED_TX_BM_EN |
515 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
516 - } else {
517 - wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
518 - if (mtk_wed_get_rx_capa(dev)) {
519 - /* rx hw init */
520 - wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
521 - MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
522 - MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
523 - wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
524 -
525 - mtk_wed_rx_buffer_hw_init(dev);
526 - mtk_wed_rro_hw_init(dev);
527 - mtk_wed_route_qm_hw_init(dev);
528 - }
529 + } else if (mtk_wed_get_rx_capa(dev)) {
530 + /* rx hw init */
531 + wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
532 + MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
533 + MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
534 + wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
535 +
536 + /* reset prefetch index of ring */
537 + wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
538 + MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
539 + wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
540 + MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
541 +
542 + wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
543 + MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
544 + wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
545 + MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
546 +
547 + /* reset prefetch FIFO of ring */
548 + wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG,
549 + MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR |
550 + MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR);
551 + wed_w32(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG, 0);
552 +
553 + mtk_wed_rx_buffer_hw_init(dev);
554 + mtk_wed_rro_hw_init(dev);
555 + mtk_wed_route_qm_hw_init(dev);
556 }
557
558 wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
559 + if (!mtk_wed_is_v1(dev->hw))
560 + wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
561 }
562
563 static void
564 @@ -1303,6 +1413,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
565 dev->hw->soc->wdma_desc_size, true))
566 return -ENOMEM;
567
568 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
569 + struct mtk_wdma_desc *desc = wdma->desc;
570 + int i;
571 +
572 + for (i = 0; i < MTK_WED_WDMA_RING_SIZE; i++) {
573 + desc->buf0 = 0;
574 + desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
575 + desc->buf1 = 0;
576 + desc->info = cpu_to_le32(MTK_WDMA_TXD0_DESC_INFO_DMA_DONE);
577 + desc++;
578 + desc->buf0 = 0;
579 + desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
580 + desc->buf1 = 0;
581 + desc->info = cpu_to_le32(MTK_WDMA_TXD1_DESC_INFO_DMA_DONE);
582 + desc++;
583 + }
584 + }
585 +
586 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
587 wdma->desc_phys);
588 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
589 @@ -1368,6 +1496,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
590
591 wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
592 } else {
593 + if (mtk_wed_is_v3_or_greater(dev->hw))
594 + wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_TKID_ALI_EN);
595 +
596 /* initail tx interrupt trigger */
597 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
598 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
599 @@ -1420,33 +1551,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
600 {
601 int i;
602
603 - wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
604 + if (!mtk_wed_is_v3_or_greater(dev->hw)) {
605 + wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
606 + MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
607 + wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
608 + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
609 + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
610 + wdma_set(dev, MTK_WDMA_GLO_CFG,
611 + MTK_WDMA_GLO_CFG_TX_DMA_EN |
612 + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
613 + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
614 + wed_set(dev, MTK_WED_WPDMA_CTRL, MTK_WED_WPDMA_CTRL_SDL1_FIXED);
615 + } else {
616 + wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
617 + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
618 + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN |
619 + MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR);
620 + wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
621 + }
622
623 wed_set(dev, MTK_WED_GLO_CFG,
624 MTK_WED_GLO_CFG_TX_DMA_EN |
625 MTK_WED_GLO_CFG_RX_DMA_EN);
626 - wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
627 - MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
628 - MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
629 +
630 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
631 MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
632
633 - wdma_set(dev, MTK_WDMA_GLO_CFG,
634 - MTK_WDMA_GLO_CFG_TX_DMA_EN |
635 - MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
636 - MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
637 -
638 if (mtk_wed_is_v1(dev->hw)) {
639 wdma_set(dev, MTK_WDMA_GLO_CFG,
640 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
641 return;
642 }
643
644 - wed_set(dev, MTK_WED_WPDMA_CTRL,
645 - MTK_WED_WPDMA_CTRL_SDL1_FIXED);
646 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
647 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
648 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
649 +
650 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
651 + wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
652 + FIELD_PREP(MTK_WED_WDMA_RX_PREF_BURST_SIZE, 0x10) |
653 + FIELD_PREP(MTK_WED_WDMA_RX_PREF_LOW_THRES, 0x8));
654 + wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
655 + MTK_WED_WDMA_RX_PREF_DDONE2_EN);
656 + wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG, MTK_WED_WDMA_RX_PREF_EN);
657 +
658 + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
659 + MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST);
660 + wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
661 + MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK |
662 + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK |
663 + MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
664 +
665 + wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
666 + }
667 +
668 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
669 MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
670 MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
671 @@ -1458,11 +1616,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
672 MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
673 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
674
675 + wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RXD_READ_LEN);
676 wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
677 MTK_WED_WPDMA_RX_D_RX_DRV_EN |
678 FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
679 - FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
680 - 0x2));
681 + FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL, 0x2));
682 +
683 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
684 + wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
685 + MTK_WED_WPDMA_RX_D_PREF_EN |
686 + FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE, 0x10) |
687 + FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_LOW_THRES, 0x8));
688 +
689 + wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_RX_D_DRV_EN);
690 + wdma_set(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
691 + wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
692 + }
693
694 for (i = 0; i < MTK_WED_RX_QUEUES; i++)
695 mtk_wed_check_wfdma_rx_fill(dev, i);
696 @@ -1502,6 +1671,12 @@ mtk_wed_start(struct mtk_wed_device *dev
697 wed_r32(dev, MTK_WED_EXT_INT_MASK1);
698 wed_r32(dev, MTK_WED_EXT_INT_MASK2);
699
700 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
701 + wed_w32(dev, MTK_WED_EXT_INT_MASK3,
702 + MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
703 + wed_r32(dev, MTK_WED_EXT_INT_MASK3);
704 + }
705 +
706 if (mtk_wed_rro_cfg(dev))
707 return;
708 }
709 @@ -1553,6 +1728,7 @@ mtk_wed_attach(struct mtk_wed_device *de
710 dev->irq = hw->irq;
711 dev->wdma_idx = hw->index;
712 dev->version = hw->version;
713 + dev->hw->pcie_base = mtk_wed_get_pcie_base(dev);
714
715 if (hw->eth->dma_dev == hw->eth->dev &&
716 of_dma_is_coherent(hw->eth->dev->of_node))
717 @@ -1620,6 +1796,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
718 ring->reg_base = MTK_WED_RING_TX(idx);
719 ring->wpdma = regs;
720
721 + if (mtk_wed_is_v3_or_greater(dev->hw) && idx == 1) {
722 + /* reset prefetch index */
723 + wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
724 + MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
725 + MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
726 +
727 + wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
728 + MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
729 + MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
730 +
731 + /* reset prefetch FIFO */
732 + wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG,
733 + MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR |
734 + MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR);
735 + wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, 0);
736 + }
737 +
738 /* WED -> WPDMA */
739 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
740 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
741 @@ -1694,15 +1887,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
742 static u32
743 mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
744 {
745 - u32 val, ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
746 + u32 val, ext_mask;
747
748 - if (mtk_wed_is_v1(dev->hw))
749 - ext_mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
750 + if (mtk_wed_is_v3_or_greater(dev->hw))
751 + ext_mask = MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
752 + MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
753 else
754 - ext_mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
755 - MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH |
756 - MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
757 - MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR;
758 + ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
759
760 val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
761 wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
762 @@ -1943,6 +2134,9 @@ void mtk_wed_add_hw(struct device_node *
763 case 2:
764 hw->soc = &mt7986_data;
765 break;
766 + case 3:
767 + hw->soc = &mt7988_data;
768 + break;
769 default:
770 case 1:
771 hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
772 --- a/drivers/net/ethernet/mediatek/mtk_wed.h
773 +++ b/drivers/net/ethernet/mediatek/mtk_wed.h
774 @@ -9,6 +9,8 @@
775 #include <linux/regmap.h>
776 #include <linux/netdevice.h>
777
778 +#include "mtk_wed_regs.h"
779 +
780 struct mtk_eth;
781 struct mtk_wed_wo;
782
783 @@ -19,6 +21,7 @@ struct mtk_wed_soc_data {
784 u32 reset_idx_tx_mask;
785 u32 reset_idx_rx_mask;
786 } regmap;
787 + u32 tx_ring_desc_size;
788 u32 wdma_desc_size;
789 };
790
791 @@ -35,6 +38,7 @@ struct mtk_wed_hw {
792 struct dentry *debugfs_dir;
793 struct mtk_wed_device *wed_dev;
794 struct mtk_wed_wo *wed_wo;
795 + u32 pcie_base;
796 u32 debugfs_reg;
797 u32 num_flows;
798 u8 version;
799 @@ -61,6 +65,16 @@ static inline bool mtk_wed_is_v2(struct
800 return hw->version == 2;
801 }
802
803 +static inline bool mtk_wed_is_v3(struct mtk_wed_hw *hw)
804 +{
805 + return hw->version == 3;
806 +}
807 +
808 +static inline bool mtk_wed_is_v3_or_greater(struct mtk_wed_hw *hw)
809 +{
810 + return hw->version > 2;
811 +}
812 +
813 static inline void
814 wed_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
815 {
816 @@ -143,6 +157,21 @@ wpdma_txfree_w32(struct mtk_wed_device *
817 writel(val, dev->txfree_ring.wpdma + reg);
818 }
819
820 +static inline u32 mtk_wed_get_pcie_base(struct mtk_wed_device *dev)
821 +{
822 + if (!mtk_wed_is_v3_or_greater(dev->hw))
823 + return MTK_WED_PCIE_BASE;
824 +
825 + switch (dev->hw->index) {
826 + case 1:
827 + return MTK_WED_PCIE_BASE1;
828 + case 2:
829 + return MTK_WED_PCIE_BASE2;
830 + default:
831 + return MTK_WED_PCIE_BASE0;
832 + }
833 +}
834 +
835 void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
836 void __iomem *wdma, phys_addr_t wdma_phy,
837 int index);
838 --- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
839 +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
840 @@ -331,10 +331,22 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
841 wo->hw->index + 1);
842
843 /* load firmware */
844 - if (of_device_is_compatible(wo->hw->node, "mediatek,mt7981-wed"))
845 - fw_name = MT7981_FIRMWARE_WO;
846 - else
847 - fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1 : MT7986_FIRMWARE_WO0;
848 + switch (wo->hw->version) {
849 + case 2:
850 + if (of_device_is_compatible(wo->hw->node,
851 + "mediatek,mt7981-wed"))
852 + fw_name = MT7981_FIRMWARE_WO;
853 + else
854 + fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1
855 + : MT7986_FIRMWARE_WO0;
856 + break;
857 + case 3:
858 + fw_name = wo->hw->index ? MT7988_FIRMWARE_WO1
859 + : MT7988_FIRMWARE_WO0;
860 + break;
861 + default:
862 + return -EINVAL;
863 + }
864
865 ret = request_firmware(&fw, fw_name, wo->hw->dev);
866 if (ret)
867 @@ -355,15 +367,16 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
868 }
869
870 /* set the start address */
871 - boot_cr = wo->hw->index ? MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR
872 - : MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
873 + if (!mtk_wed_is_v3_or_greater(wo->hw) && wo->hw->index)
874 + boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR;
875 + else
876 + boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
877 wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
878 /* wo firmware reset */
879 wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
880
881 - val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR);
882 - val |= wo->hw->index ? MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK
883 - : MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
884 + val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
885 + MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
886 wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
887 out:
888 release_firmware(fw);
889 @@ -398,3 +411,5 @@ int mtk_wed_mcu_init(struct mtk_wed_wo *
890 MODULE_FIRMWARE(MT7981_FIRMWARE_WO);
891 MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
892 MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);
893 +MODULE_FIRMWARE(MT7988_FIRMWARE_WO0);
894 +MODULE_FIRMWARE(MT7988_FIRMWARE_WO1);
895 --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
896 +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
897 @@ -13,6 +13,9 @@
898 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
899 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
900
901 +#define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29)
902 +#define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31)
903 +
904 struct mtk_wdma_desc {
905 __le32 buf0;
906 __le32 ctrl;
907 @@ -37,6 +40,7 @@ struct mtk_wdma_desc {
908 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
909 #define MTK_WED_RESET_RX_RRO_QM BIT(20)
910 #define MTK_WED_RESET_RX_ROUTE_QM BIT(21)
911 +#define MTK_WED_RESET_TX_AMSDU BIT(22)
912 #define MTK_WED_RESET_WED BIT(31)
913
914 #define MTK_WED_CTRL 0x00c
915 @@ -44,6 +48,9 @@ struct mtk_wdma_desc {
916 #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1)
917 #define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2)
918 #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3)
919 +#define MTK_WED_CTRL_WED_RX_IND_CMD_EN BIT(5)
920 +#define MTK_WED_CTRL_WED_RX_PG_BM_EN BIT(6)
921 +#define MTK_WED_CTRL_WED_RX_PG_BM_BUSY BIT(7)
922 #define MTK_WED_CTRL_WED_TX_BM_EN BIT(8)
923 #define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)
924 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)
925 @@ -54,9 +61,14 @@ struct mtk_wdma_desc {
926 #define MTK_WED_CTRL_RX_RRO_QM_BUSY BIT(15)
927 #define MTK_WED_CTRL_RX_ROUTE_QM_EN BIT(16)
928 #define MTK_WED_CTRL_RX_ROUTE_QM_BUSY BIT(17)
929 +#define MTK_WED_CTRL_TX_TKID_ALI_EN BIT(20)
930 +#define MTK_WED_CTRL_TX_TKID_ALI_BUSY BIT(21)
931 +#define MTK_WED_CTRL_TX_AMSDU_EN BIT(22)
932 +#define MTK_WED_CTRL_TX_AMSDU_BUSY BIT(23)
933 #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
934 #define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)
935 #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
936 +#define MTK_WED_CTRL_FLD_MIB_RD_CLR BIT(28)
937
938 #define MTK_WED_EXT_INT_STATUS 0x020
939 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
940 @@ -89,6 +101,7 @@ struct mtk_wdma_desc {
941 #define MTK_WED_EXT_INT_MASK 0x028
942 #define MTK_WED_EXT_INT_MASK1 0x02c
943 #define MTK_WED_EXT_INT_MASK2 0x030
944 +#define MTK_WED_EXT_INT_MASK3 0x034
945
946 #define MTK_WED_STATUS 0x060
947 #define MTK_WED_STATUS_TX GENMASK(15, 8)
948 @@ -96,9 +109,14 @@ struct mtk_wdma_desc {
949 #define MTK_WED_TX_BM_CTRL 0x080
950 #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0)
951 #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)
952 +#define MTK_WED_TX_BM_CTRL_LEGACY_EN BIT(26)
953 +#define MTK_WED_TX_TKID_CTRL_FREE_FORMAT BIT(27)
954 #define MTK_WED_TX_BM_CTRL_PAUSE BIT(28)
955
956 #define MTK_WED_TX_BM_BASE 0x084
957 +#define MTK_WED_TX_BM_INIT_PTR 0x088
958 +#define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0)
959 +#define MTK_WED_TX_BM_INIT_SW_TAIL_IDX BIT(16)
960
961 #define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
962 #define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
963 @@ -122,6 +140,9 @@ struct mtk_wdma_desc {
964 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16)
965 #define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28)
966
967 +#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3 GENMASK(7, 0)
968 +#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3 GENMASK(23, 16)
969 +
970 #define MTK_WED_TX_TKID_DYN_THR 0x0e0
971 #define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0)
972 #define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16)
973 @@ -199,12 +220,15 @@ struct mtk_wdma_desc {
974 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5)
975 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6)
976 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7)
977 -#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(18, 16)
978 +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(15, 12)
979 +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4 BIT(18)
980 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19)
981 -#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20)
982 +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK BIT(20)
983 #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21)
984 #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24)
985 +#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST BIT(25)
986 #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28)
987 +#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30)
988
989 #define MTK_WED_WPDMA_RESET_IDX 0x50c
990 #define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0)
991 @@ -250,9 +274,10 @@ struct mtk_wdma_desc {
992 #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16)
993
994 #define MTK_WED_PCIE_INT_CTRL 0x57c
995 -#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
996 -#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)
997 #define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12)
998 +#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)
999 +#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
1000 +#define MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER BIT(21)
1001
1002 #define MTK_WED_WPDMA_CFG_BASE 0x580
1003 #define MTK_WED_WPDMA_CFG_INT_MASK 0x584
1004 @@ -286,6 +311,20 @@ struct mtk_wdma_desc {
1005 #define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n) (0x784 + (_n) * 4)
1006 #define MTK_WED_WPDMA_RX_D_COHERENT_MIB 0x78c
1007
1008 +#define MTK_WED_WPDMA_RX_D_PREF_CFG 0x7b4
1009 +#define MTK_WED_WPDMA_RX_D_PREF_EN BIT(0)
1010 +#define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE GENMASK(12, 8)
1011 +#define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES GENMASK(21, 16)
1012 +
1013 +#define MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX 0x7b8
1014 +#define MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR BIT(15)
1015 +
1016 +#define MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX 0x7bc
1017 +
1018 +#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG 0x7c0
1019 +#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR BIT(0)
1020 +#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR BIT(16)
1021 +
1022 #define MTK_WED_WDMA_RING_TX 0x800
1023
1024 #define MTK_WED_WDMA_TX_MIB 0x810
1025 @@ -293,6 +332,18 @@ struct mtk_wdma_desc {
1026 #define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10)
1027 #define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4)
1028
1029 +#define MTK_WED_WDMA_RX_PREF_CFG 0x950
1030 +#define MTK_WED_WDMA_RX_PREF_EN BIT(0)
1031 +#define MTK_WED_WDMA_RX_PREF_BURST_SIZE GENMASK(12, 8)
1032 +#define MTK_WED_WDMA_RX_PREF_LOW_THRES GENMASK(21, 16)
1033 +#define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR BIT(24)
1034 +#define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR BIT(25)
1035 +#define MTK_WED_WDMA_RX_PREF_DDONE2_EN BIT(26)
1036 +
1037 +#define MTK_WED_WDMA_RX_PREF_FIFO_CFG 0x95C
1038 +#define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR BIT(0)
1039 +#define MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR BIT(16)
1040 +
1041 #define MTK_WED_WDMA_GLO_CFG 0xa04
1042 #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
1043 #define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK BIT(1)
1044 @@ -325,6 +376,7 @@ struct mtk_wdma_desc {
1045 #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16)
1046
1047 #define MTK_WED_WDMA_INT_CTRL 0xa2c
1048 +#define MTK_WED_WDMA_INT_POLL_PRD GENMASK(7, 0)
1049 #define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16)
1050
1051 #define MTK_WED_WDMA_CFG_BASE 0xaa0
1052 @@ -388,6 +440,18 @@ struct mtk_wdma_desc {
1053 #define MTK_WDMA_INT_GRP1 0x250
1054 #define MTK_WDMA_INT_GRP2 0x254
1055
1056 +#define MTK_WDMA_PREF_TX_CFG 0x2d0
1057 +#define MTK_WDMA_PREF_TX_CFG_PREF_EN BIT(0)
1058 +
1059 +#define MTK_WDMA_PREF_RX_CFG 0x2dc
1060 +#define MTK_WDMA_PREF_RX_CFG_PREF_EN BIT(0)
1061 +
1062 +#define MTK_WDMA_WRBK_TX_CFG 0x300
1063 +#define MTK_WDMA_WRBK_TX_CFG_WRBK_EN BIT(30)
1064 +
1065 +#define MTK_WDMA_WRBK_RX_CFG 0x344
1066 +#define MTK_WDMA_WRBK_RX_CFG_WRBK_EN BIT(30)
1067 +
1068 #define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0)
1069 #define MTK_PCIE_MIRROR_MAP_EN BIT(0)
1070 #define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1)
1071 @@ -401,6 +465,30 @@ struct mtk_wdma_desc {
1072 #define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5)
1073 #define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20)
1074
1075 +#define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT 0xb1c
1076 +#define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n) (0xb20 + (_n) * 0x4)
1077 +#define MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT 0xb28
1078 +#define MTK_WED_RTQM_IGRS0_I2H_PKT_CNT(_n) (0xb2c + (_n) * 0x4)
1079 +#define MTK_WED_RTQM_IGRS0_FDROP_CNT 0xb34
1080 +
1081 +#define MTK_WED_RTQM_IGRS1_I2HW_DMAD_CNT 0xb44
1082 +#define MTK_WED_RTQM_IGRS1_I2H_DMAD_CNT(_n) (0xb48 + (_n) * 0x4)
1083 +#define MTK_WED_RTQM_IGRS1_I2HW_PKT_CNT 0xb50
1084 +#define MTK_WED_RTQM_IGRS1_I2H_PKT_CNT(_n) (0xb54 + (_n) * 0x4)
1085 +#define MTK_WED_RTQM_IGRS1_FDROP_CNT 0xb5c
1086 +
1087 +#define MTK_WED_RTQM_IGRS2_I2HW_DMAD_CNT 0xb6c
1088 +#define MTK_WED_RTQM_IGRS2_I2H_DMAD_CNT(_n) (0xb70 + (_n) * 0x4)
1089 +#define MTK_WED_RTQM_IGRS2_I2HW_PKT_CNT 0xb78
1090 +#define MTK_WED_RTQM_IGRS2_I2H_PKT_CNT(_n) (0xb7c + (_n) * 0x4)
1091 +#define MTK_WED_RTQM_IGRS2_FDROP_CNT 0xb84
1092 +
1093 +#define MTK_WED_RTQM_IGRS3_I2HW_DMAD_CNT 0xb94
1094 +#define MTK_WED_RTQM_IGRS3_I2H_DMAD_CNT(_n) (0xb98 + (_n) * 0x4)
1095 +#define MTK_WED_RTQM_IGRS3_I2HW_PKT_CNT 0xba0
1096 +#define MTK_WED_RTQM_IGRS3_I2H_PKT_CNT(_n) (0xba4 + (_n) * 0x4)
1097 +#define MTK_WED_RTQM_IGRS3_FDROP_CNT 0xbac
1098 +
1099 #define MTK_WED_RTQM_R2H_MIB(_n) (0xb70 + (_n) * 0x4)
1100 #define MTK_WED_RTQM_R2Q_MIB(_n) (0xb78 + (_n) * 0x4)
1101 #define MTK_WED_RTQM_Q2N_MIB 0xb80
1102 @@ -409,6 +497,24 @@ struct mtk_wdma_desc {
1103 #define MTK_WED_RTQM_Q2B_MIB 0xb8c
1104 #define MTK_WED_RTQM_PFDBK_MIB 0xb90
1105
1106 +#define MTK_WED_RTQM_ENQ_CFG0 0xbb8
1107 +#define MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT GENMASK(15, 12)
1108 +
1109 +#define MTK_WED_RTQM_FDROP_MIB 0xb84
1110 +#define MTK_WED_RTQM_ENQ_I2Q_DMAD_CNT 0xbbc
1111 +#define MTK_WED_RTQM_ENQ_I2N_DMAD_CNT 0xbc0
1112 +#define MTK_WED_RTQM_ENQ_I2Q_PKT_CNT 0xbc4
1113 +#define MTK_WED_RTQM_ENQ_I2N_PKT_CNT 0xbc8
1114 +#define MTK_WED_RTQM_ENQ_USED_ENTRY_CNT 0xbcc
1115 +#define MTK_WED_RTQM_ENQ_ERR_CNT 0xbd0
1116 +
1117 +#define MTK_WED_RTQM_DEQ_DMAD_CNT 0xbd8
1118 +#define MTK_WED_RTQM_DEQ_Q2I_DMAD_CNT 0xbdc
1119 +#define MTK_WED_RTQM_DEQ_PKT_CNT 0xbe0
1120 +#define MTK_WED_RTQM_DEQ_Q2I_PKT_CNT 0xbe4
1121 +#define MTK_WED_RTQM_DEQ_USED_PFDBK_CNT 0xbe8
1122 +#define MTK_WED_RTQM_DEQ_ERR_CNT 0xbec
1123 +
1124 #define MTK_WED_RROQM_GLO_CFG 0xc04
1125 #define MTK_WED_RROQM_RST_IDX 0xc08
1126 #define MTK_WED_RROQM_RST_IDX_MIOD BIT(0)
1127 @@ -458,7 +564,116 @@ struct mtk_wdma_desc {
1128 #define MTK_WED_RX_BM_INTF 0xd9c
1129 #define MTK_WED_RX_BM_ERR_STS 0xda8
1130
1131 +#define MTK_RRO_IND_CMD_SIGNATURE 0xe00
1132 +#define MTK_RRO_IND_CMD_DMA_IDX GENMASK(11, 0)
1133 +#define MTK_RRO_IND_CMD_MAGIC_CNT GENMASK(30, 28)
1134 +
1135 +#define MTK_WED_IND_CMD_RX_CTRL0 0xe04
1136 +#define MTK_WED_IND_CMD_PROC_IDX GENMASK(11, 0)
1137 +#define MTK_WED_IND_CMD_PREFETCH_FREE_CNT GENMASK(19, 16)
1138 +#define MTK_WED_IND_CMD_MAGIC_CNT GENMASK(30, 28)
1139 +
1140 +#define MTK_WED_IND_CMD_RX_CTRL1 0xe08
1141 +#define MTK_WED_IND_CMD_RX_CTRL2 0xe0c
1142 +#define MTK_WED_IND_CMD_MAX_CNT GENMASK(11, 0)
1143 +#define MTK_WED_IND_CMD_BASE_M GENMASK(19, 16)
1144 +
1145 +#define MTK_WED_RRO_CFG0 0xe10
1146 +#define MTK_WED_RRO_CFG1 0xe14
1147 +#define MTK_WED_RRO_CFG1_MAX_WIN_SZ GENMASK(31, 29)
1148 +#define MTK_WED_RRO_CFG1_ACK_SN_BASE_M GENMASK(19, 16)
1149 +#define MTK_WED_RRO_CFG1_PARTICL_SE_ID GENMASK(11, 0)
1150 +
1151 +#define MTK_WED_ADDR_ELEM_CFG0 0xe18
1152 +#define MTK_WED_ADDR_ELEM_CFG1 0xe1c
1153 +#define MTK_WED_ADDR_ELEM_PREFETCH_FREE_CNT GENMASK(19, 16)
1154 +
1155 +#define MTK_WED_ADDR_ELEM_TBL_CFG 0xe20
1156 +#define MTK_WED_ADDR_ELEM_TBL_OFFSET GENMASK(6, 0)
1157 +#define MTK_WED_ADDR_ELEM_TBL_RD_RDY BIT(28)
1158 +#define MTK_WED_ADDR_ELEM_TBL_WR_RDY BIT(29)
1159 +#define MTK_WED_ADDR_ELEM_TBL_RD BIT(30)
1160 +#define MTK_WED_ADDR_ELEM_TBL_WR BIT(31)
1161 +
1162 +#define MTK_WED_RADDR_ELEM_TBL_WDATA 0xe24
1163 +#define MTK_WED_RADDR_ELEM_TBL_RDATA 0xe28
1164 +
1165 +#define MTK_WED_PN_CHECK_CFG 0xe30
1166 +#define MTK_WED_PN_CHECK_SE_ID GENMASK(11, 0)
1167 +#define MTK_WED_PN_CHECK_RD_RDY BIT(28)
1168 +#define MTK_WED_PN_CHECK_WR_RDY BIT(29)
1169 +#define MTK_WED_PN_CHECK_RD BIT(30)
1170 +#define MTK_WED_PN_CHECK_WR BIT(31)
1171 +
1172 +#define MTK_WED_PN_CHECK_WDATA_M 0xe38
1173 +#define MTK_WED_PN_CHECK_IS_FIRST BIT(17)
1174 +
1175 +#define MTK_WED_RRO_MSDU_PG_RING_CFG(_n) (0xe44 + (_n) * 0x8)
1176 +
1177 +#define MTK_WED_RRO_MSDU_PG_RING2_CFG 0xe58
1178 +#define MTK_WED_RRO_MSDU_PG_DRV_CLR BIT(26)
1179 +#define MTK_WED_RRO_MSDU_PG_DRV_EN BIT(31)
1180 +
1181 +#define MTK_WED_RRO_MSDU_PG_CTRL0(_n) (0xe5c + (_n) * 0xc)
1182 +#define MTK_WED_RRO_MSDU_PG_CTRL1(_n) (0xe60 + (_n) * 0xc)
1183 +#define MTK_WED_RRO_MSDU_PG_CTRL2(_n) (0xe64 + (_n) * 0xc)
1184 +
1185 +#define MTK_WED_RRO_RX_D_RX(_n) (0xe80 + (_n) * 0x10)
1186 +
1187 +#define MTK_WED_RRO_RX_MAGIC_CNT BIT(13)
1188 +
1189 +#define MTK_WED_RRO_RX_D_CFG(_n) (0xea0 + (_n) * 0x4)
1190 +#define MTK_WED_RRO_RX_D_DRV_CLR BIT(26)
1191 +#define MTK_WED_RRO_RX_D_DRV_EN BIT(31)
1192 +
1193 +#define MTK_WED_RRO_PG_BM_RX_DMAM 0xeb0
1194 +#define MTK_WED_RRO_PG_BM_RX_SDL0 GENMASK(13, 0)
1195 +
1196 +#define MTK_WED_RRO_PG_BM_BASE 0xeb4
1197 +#define MTK_WED_RRO_PG_BM_INIT_PTR 0xeb8
1198 +#define MTK_WED_RRO_PG_BM_SW_TAIL_IDX GENMASK(15, 0)
1199 +#define MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX BIT(16)
1200 +
1201 +#define MTK_WED_WPDMA_INT_CTRL_RRO_RX 0xeec
1202 +#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN BIT(0)
1203 +#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR BIT(1)
1204 +#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG GENMASK(6, 2)
1205 +#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN BIT(8)
1206 +#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR BIT(9)
1207 +#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG GENMASK(14, 10)
1208 +
1209 +#define MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG 0xef4
1210 +#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN BIT(0)
1211 +#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR BIT(1)
1212 +#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG GENMASK(6, 2)
1213 +#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN BIT(8)
1214 +#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR BIT(9)
1215 +#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG GENMASK(14, 10)
1216 +#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN BIT(16)
1217 +#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR BIT(17)
1218 +#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG GENMASK(22, 18)
1219 +
1220 +#define MTK_WED_RX_IND_CMD_CNT0 0xf20
1221 +#define MTK_WED_RX_IND_CMD_DBG_CNT_EN BIT(31)
1222 +
1223 +#define MTK_WED_RX_IND_CMD_CNT(_n) (0xf20 + (_n) * 0x4)
1224 +#define MTK_WED_IND_CMD_MAGIC_CNT_FAIL_CNT GENMASK(15, 0)
1225 +
1226 +#define MTK_WED_RX_ADDR_ELEM_CNT(_n) (0xf48 + (_n) * 0x4)
1227 +#define MTK_WED_ADDR_ELEM_SIG_FAIL_CNT GENMASK(15, 0)
1228 +#define MTK_WED_ADDR_ELEM_FIRST_SIG_FAIL_CNT GENMASK(31, 16)
1229 +#define MTK_WED_ADDR_ELEM_ACKSN_CNT GENMASK(27, 0)
1230 +
1231 +#define MTK_WED_RX_MSDU_PG_CNT(_n) (0xf5c + (_n) * 0x4)
1232 +
1233 +#define MTK_WED_RX_PN_CHK_CNT 0xf70
1234 +#define MTK_WED_PN_CHK_FAIL_CNT GENMASK(15, 0)
1235 +
1236 #define MTK_WED_WOCPU_VIEW_MIOD_BASE 0x8000
1237 #define MTK_WED_PCIE_INT_MASK 0x0
1238
1239 +#define MTK_WED_PCIE_BASE 0x11280000
1240 +#define MTK_WED_PCIE_BASE0 0x11300000
1241 +#define MTK_WED_PCIE_BASE1 0x11310000
1242 +#define MTK_WED_PCIE_BASE2 0x11290000
1243 #endif
1244 --- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
1245 +++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
1246 @@ -91,6 +91,8 @@ enum mtk_wed_dummy_cr_idx {
1247 #define MT7981_FIRMWARE_WO "mediatek/mt7981_wo.bin"
1248 #define MT7986_FIRMWARE_WO0 "mediatek/mt7986_wo_0.bin"
1249 #define MT7986_FIRMWARE_WO1 "mediatek/mt7986_wo_1.bin"
1250 +#define MT7988_FIRMWARE_WO0 "mediatek/mt7988_wo_0.bin"
1251 +#define MT7988_FIRMWARE_WO1 "mediatek/mt7988_wo_1.bin"
1252
1253 #define MTK_WO_MCU_CFG_LS_BASE 0
1254 #define MTK_WO_MCU_CFG_LS_HW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x000)
1255 --- a/include/linux/soc/mediatek/mtk_wed.h
1256 +++ b/include/linux/soc/mediatek/mtk_wed.h
1257 @@ -138,6 +138,8 @@ struct mtk_wed_device {
1258 u32 wpdma_rx;
1259
1260 bool wcid_512;
1261 + bool hw_rro;
1262 + bool msi;
1263
1264 u16 token_start;
1265 unsigned int nbuf;
1266 @@ -211,10 +213,12 @@ mtk_wed_device_attach(struct mtk_wed_dev
1267 return ret;
1268 }
1269
1270 -static inline bool
1271 -mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
1272 +static inline bool mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
1273 {
1274 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
1275 + if (dev->version == 3)
1276 + return dev->wlan.hw_rro;
1277 +
1278 return dev->version != 1;
1279 #else
1280 return false;
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