target/linux/generic/backport-6.1/790-02-v6.4-net-dsa-mt7530-use-external-PCS-driver.patch

   1 From 05dc5ea089f947a69a5db092ef4cad6a0f3c96ce Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Sun, 19 Mar 2023 12:58:43 +0000
   4 Subject: [PATCH 02/48] net: dsa: mt7530: use external PCS driver
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Implement regmap access wrappers, for now only to be used by the
  10 pcs-mtk-lynxi driver.
  11 Make use of this external PCS driver and drop the now reduntant
  12 implementation in mt7530.c.
  13 As a nice side effect the SGMII registers can now also more easily be
  14 inspected for debugging via /sys/kernel/debug/regmap.
  15
  16 Tested-by: Bjørn Mork <bjorn@mork.no>
  17 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  18 Tested-by: Frank Wunderlich <frank-w@public-files.de>
  19 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  20 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  21 ---
  22  drivers/net/dsa/Kconfig  |   1 +
  23  drivers/net/dsa/mt7530.c | 277 ++++++++++-----------------------------
  24  drivers/net/dsa/mt7530.h |  47 +------
  25  3 files changed, 71 insertions(+), 254 deletions(-)
  26
  27 --- a/drivers/net/dsa/Kconfig
  28 +++ b/drivers/net/dsa/Kconfig
  29 @@ -37,6 +37,7 @@ config NET_DSA_MT7530
  30         tristate "MediaTek MT753x and MT7621 Ethernet switch support"
  31         select NET_DSA_TAG_MTK
  32         select MEDIATEK_GE_PHY
  33 +       select PCS_MTK_LYNXI
  34         help
  35           This enables support for the MediaTek MT7530, MT7531, and MT7621
  36           Ethernet switch chips.
  37 --- a/drivers/net/dsa/mt7530.c
  38 +++ b/drivers/net/dsa/mt7530.c
  39 @@ -14,6 +14,7 @@
  40  #include <linux/of_mdio.h>
  41  #include <linux/of_net.h>
  42  #include <linux/of_platform.h>
  43 +#include <linux/pcs/pcs-mtk-lynxi.h>
  44  #include <linux/phylink.h>
  45  #include <linux/regmap.h>
  46  #include <linux/regulator/consumer.h>
  47 @@ -2651,128 +2652,11 @@ static int mt7531_rgmii_setup(struct mt7
  48         return 0;
  49  }
  50
  51 -static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
  52 -                              phy_interface_t interface, int speed, int duplex)
  53 -{
  54 -       struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
  55 -       int port = pcs_to_mt753x_pcs(pcs)->port;
  56 -       unsigned int val;
  57 -
  58 -       /* For adjusting speed and duplex of SGMII force mode. */
  59 -       if (interface != PHY_INTERFACE_MODE_SGMII ||
  60 -           phylink_autoneg_inband(mode))
  61 -               return;
  62 -
  63 -       /* SGMII force mode setting */
  64 -       val = mt7530_read(priv, MT7531_SGMII_MODE(port));
  65 -       val &= ~MT7531_SGMII_IF_MODE_MASK;
  66 -
  67 -       switch (speed) {
  68 -       case SPEED_10:
  69 -               val |= MT7531_SGMII_FORCE_SPEED_10;
  70 -               break;
  71 -       case SPEED_100:
  72 -               val |= MT7531_SGMII_FORCE_SPEED_100;
  73 -               break;
  74 -       case SPEED_1000:
  75 -               val |= MT7531_SGMII_FORCE_SPEED_1000;
  76 -               break;
  77 -       }
  78 -
  79 -       /* MT7531 SGMII 1G force mode can only work in full duplex mode,
  80 -        * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
  81 -        *
  82 -        * The speed check is unnecessary as the MAC capabilities apply
  83 -        * this restriction. --rmk
  84 -        */
  85 -       if ((speed == SPEED_10 || speed == SPEED_100) &&
  86 -           duplex != DUPLEX_FULL)
  87 -               val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
  88 -
  89 -       mt7530_write(priv, MT7531_SGMII_MODE(port), val);
  90 -}
  91 -
  92  static bool mt753x_is_mac_port(u32 port)
  93  {
  94         return (port == 5 || port == 6);
  95  }
  96
  97 -static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
  98 -                                        phy_interface_t interface)
  99 -{
 100 -       u32 val;
 101 -
 102 -       if (!mt753x_is_mac_port(port))
 103 -               return -EINVAL;
 104 -
 105 -       mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
 106 -                  MT7531_SGMII_PHYA_PWD);
 107 -
 108 -       val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
 109 -       val &= ~MT7531_RG_TPHY_SPEED_MASK;
 110 -       /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
 111 -        * encoding.
 112 -        */
 113 -       val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
 114 -               MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
 115 -       mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
 116 -
 117 -       mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
 118 -
 119 -       /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
 120 -        * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
 121 -        */
 122 -       mt7530_rmw(priv, MT7531_SGMII_MODE(port),
 123 -                  MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
 124 -                  MT7531_SGMII_FORCE_SPEED_1000);
 125 -
 126 -       mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
 127 -
 128 -       return 0;
 129 -}
 130 -
 131 -static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
 132 -                                     phy_interface_t interface)
 133 -{
 134 -       if (!mt753x_is_mac_port(port))
 135 -               return -EINVAL;
 136 -
 137 -       mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
 138 -                  MT7531_SGMII_PHYA_PWD);
 139 -
 140 -       mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
 141 -                  MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
 142 -
 143 -       mt7530_set(priv, MT7531_SGMII_MODE(port),
 144 -                  MT7531_SGMII_REMOTE_FAULT_DIS |
 145 -                  MT7531_SGMII_SPEED_DUPLEX_AN);
 146 -
 147 -       mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
 148 -                  MT7531_SGMII_TX_CONFIG_MASK, 1);
 149 -
 150 -       mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
 151 -
 152 -       mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
 153 -
 154 -       mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
 155 -
 156 -       return 0;
 157 -}
 158 -
 159 -static void mt7531_pcs_an_restart(struct phylink_pcs *pcs)
 160 -{
 161 -       struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
 162 -       int port = pcs_to_mt753x_pcs(pcs)->port;
 163 -       u32 val;
 164 -
 165 -       /* Only restart AN when AN is enabled */
 166 -       val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
 167 -       if (val & MT7531_SGMII_AN_ENABLE) {
 168 -               val |= MT7531_SGMII_AN_RESTART;
 169 -               mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
 170 -       }
 171 -}
 172 -
 173  static int
 174  mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 175                   phy_interface_t interface)
 176 @@ -2795,11 +2679,11 @@ mt7531_mac_config(struct dsa_switch *ds,
 177                 phydev = dp->slave->phydev;
 178                 return mt7531_rgmii_setup(priv, port, interface, phydev);
 179         case PHY_INTERFACE_MODE_SGMII:
 180 -               return mt7531_sgmii_setup_mode_an(priv, port, interface);
 181         case PHY_INTERFACE_MODE_NA:
 182         case PHY_INTERFACE_MODE_1000BASEX:
 183         case PHY_INTERFACE_MODE_2500BASEX:
 184 -               return mt7531_sgmii_setup_mode_force(priv, port, interface);
 185 +               /* handled in SGMII PCS driver */
 186 +               return 0;
 187         default:
 188                 return -EINVAL;
 189         }
 190 @@ -2824,11 +2708,11 @@ mt753x_phylink_mac_select_pcs(struct dsa
 191
 192         switch (interface) {
 193         case PHY_INTERFACE_MODE_TRGMII:
 194 +               return &priv->pcs[port].pcs;
 195         case PHY_INTERFACE_MODE_SGMII:
 196         case PHY_INTERFACE_MODE_1000BASEX:
 197         case PHY_INTERFACE_MODE_2500BASEX:
 198 -               return &priv->pcs[port].pcs;
 199 -
 200 +               return priv->ports[port].sgmii_pcs;
 201         default:
 202                 return NULL;
 203         }
 204 @@ -3066,86 +2950,6 @@ static void mt7530_pcs_get_state(struct
 205                 state->pause |= MLO_PAUSE_TX;
 206  }
 207
 208 -static int
 209 -mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
 210 -                             struct phylink_link_state *state)
 211 -{
 212 -       u32 status, val;
 213 -       u16 config_reg;
 214 -
 215 -       status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
 216 -       state->link = !!(status & MT7531_SGMII_LINK_STATUS);
 217 -       state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE);
 218 -       if (state->interface == PHY_INTERFACE_MODE_SGMII &&
 219 -           (status & MT7531_SGMII_AN_ENABLE)) {
 220 -               val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
 221 -               config_reg = val >> 16;
 222 -
 223 -               switch (config_reg & LPA_SGMII_SPD_MASK) {
 224 -               case LPA_SGMII_1000:
 225 -                       state->speed = SPEED_1000;
 226 -                       break;
 227 -               case LPA_SGMII_100:
 228 -                       state->speed = SPEED_100;
 229 -                       break;
 230 -               case LPA_SGMII_10:
 231 -                       state->speed = SPEED_10;
 232 -                       break;
 233 -               default:
 234 -                       dev_err(priv->dev, "invalid sgmii PHY speed\n");
 235 -                       state->link = false;
 236 -                       return -EINVAL;
 237 -               }
 238 -
 239 -               if (config_reg & LPA_SGMII_FULL_DUPLEX)
 240 -                       state->duplex = DUPLEX_FULL;
 241 -               else
 242 -                       state->duplex = DUPLEX_HALF;
 243 -       }
 244 -
 245 -       return 0;
 246 -}
 247 -
 248 -static void
 249 -mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv *priv, int port,
 250 -                                 struct phylink_link_state *state)
 251 -{
 252 -       unsigned int val;
 253 -
 254 -       val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
 255 -       state->link = !!(val & MT7531_SGMII_LINK_STATUS);
 256 -       if (!state->link)
 257 -               return;
 258 -
 259 -       state->an_complete = state->link;
 260 -
 261 -       if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
 262 -               state->speed = SPEED_2500;
 263 -       else
 264 -               state->speed = SPEED_1000;
 265 -
 266 -       state->duplex = DUPLEX_FULL;
 267 -       state->pause = MLO_PAUSE_NONE;
 268 -}
 269 -
 270 -static void mt7531_pcs_get_state(struct phylink_pcs *pcs,
 271 -                                struct phylink_link_state *state)
 272 -{
 273 -       struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
 274 -       int port = pcs_to_mt753x_pcs(pcs)->port;
 275 -
 276 -       if (state->interface == PHY_INTERFACE_MODE_SGMII) {
 277 -               mt7531_sgmii_pcs_get_state_an(priv, port, state);
 278 -               return;
 279 -       } else if ((state->interface == PHY_INTERFACE_MODE_1000BASEX) ||
 280 -                  (state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
 281 -               mt7531_sgmii_pcs_get_state_inband(priv, port, state);
 282 -               return;
 283 -       }
 284 -
 285 -       state->link = false;
 286 -}
 287 -
 288  static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
 289                              phy_interface_t interface,
 290                              const unsigned long *advertising,
 291 @@ -3165,18 +2969,57 @@ static const struct phylink_pcs_ops mt75
 292         .pcs_an_restart = mt7530_pcs_an_restart,
 293  };
 294
 295 -static const struct phylink_pcs_ops mt7531_pcs_ops = {
 296 -       .pcs_validate = mt753x_pcs_validate,
 297 -       .pcs_get_state = mt7531_pcs_get_state,
 298 -       .pcs_config = mt753x_pcs_config,
 299 -       .pcs_an_restart = mt7531_pcs_an_restart,
 300 -       .pcs_link_up = mt7531_pcs_link_up,
 301 +static int mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
 302 +{
 303 +       struct mt7530_priv *priv = context;
 304 +
 305 +       *val = mt7530_read(priv, reg);
 306 +       return 0;
 307 +};
 308 +
 309 +static int mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
 310 +{
 311 +       struct mt7530_priv *priv = context;
 312 +
 313 +       mt7530_write(priv, reg, val);
 314 +       return 0;
 315 +};
 316 +
 317 +static int mt7530_regmap_update_bits(void *context, unsigned int reg,
 318 +                                    unsigned int mask, unsigned int val)
 319 +{
 320 +       struct mt7530_priv *priv = context;
 321 +
 322 +       mt7530_rmw(priv, reg, mask, val);
 323 +       return 0;
 324 +};
 325 +
 326 +static const struct regmap_bus mt7531_regmap_bus = {
 327 +       .reg_write = mt7530_regmap_write,
 328 +       .reg_read = mt7530_regmap_read,
 329 +       .reg_update_bits = mt7530_regmap_update_bits,
 330 +};
 331 +
 332 +#define MT7531_PCS_REGMAP_CONFIG(_name, _reg_base) \
 333 +       {                               \
 334 +               .name = _name,          \
 335 +               .reg_bits = 16,         \
 336 +               .val_bits = 32,         \
 337 +               .reg_stride = 4,        \
 338 +               .reg_base = _reg_base,  \
 339 +               .max_register = 0x17c,  \
 340 +       }
 341 +
 342 +static const struct regmap_config mt7531_pcs_config[] = {
 343 +       MT7531_PCS_REGMAP_CONFIG("port5", MT7531_SGMII_REG_BASE(5)),
 344 +       MT7531_PCS_REGMAP_CONFIG("port6", MT7531_SGMII_REG_BASE(6)),
 345  };
 346
 347  static int
 348  mt753x_setup(struct dsa_switch *ds)
 349  {
 350         struct mt7530_priv *priv = ds->priv;
 351 +       struct regmap *regmap;
 352         int i, ret;
 353
 354         /* Initialise the PCS devices */
 355 @@ -3184,8 +3027,6 @@ mt753x_setup(struct dsa_switch *ds)
 356                 priv->pcs[i].pcs.ops = priv->info->pcs_ops;
 357                 priv->pcs[i].priv = priv;
 358                 priv->pcs[i].port = i;
 359 -               if (mt753x_is_mac_port(i))
 360 -                       priv->pcs[i].pcs.poll = 1;
 361         }
 362
 363         ret = priv->info->sw_setup(ds);
 364 @@ -3200,6 +3041,16 @@ mt753x_setup(struct dsa_switch *ds)
 365         if (ret && priv->irq)
 366                 mt7530_free_irq_common(priv);
 367
 368 +       if (priv->id == ID_MT7531)
 369 +               for (i = 0; i < 2; i++) {
 370 +                       regmap = devm_regmap_init(ds->dev,
 371 +                                                 &mt7531_regmap_bus, priv,
 372 +                                                 &mt7531_pcs_config[i]);
 373 +                       priv->ports[5 + i].sgmii_pcs =
 374 +                               mtk_pcs_lynxi_create(ds->dev, regmap,
 375 +                                                    MT7531_PHYA_CTRL_SIGNAL3, 0);
 376 +               }
 377 +
 378         return ret;
 379  }
 380
 381 @@ -3291,7 +3142,7 @@ static const struct mt753x_info mt753x_t
 382         },
 383         [ID_MT7531] = {
 384                 .id = ID_MT7531,
 385 -               .pcs_ops = &mt7531_pcs_ops,
 386 +               .pcs_ops = &mt7530_pcs_ops,
 387                 .sw_setup = mt7531_setup,
 388                 .phy_read = mt7531_ind_phy_read,
 389                 .phy_write = mt7531_ind_phy_write,
 390 @@ -3399,7 +3250,7 @@ static void
 391  mt7530_remove(struct mdio_device *mdiodev)
 392  {
 393         struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
 394 -       int ret = 0;
 395 +       int ret = 0, i;
 396
 397         if (!priv)
 398                 return;
 399 @@ -3418,6 +3269,10 @@ mt7530_remove(struct mdio_device *mdiode
 400                 mt7530_free_irq(priv);
 401
 402         dsa_unregister_switch(priv->ds);
 403 +
 404 +       for (i = 0; i < 2; ++i)
 405 +               mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
 406 +
 407         mutex_destroy(&priv->reg_mutex);
 408  }
 409
 410 --- a/drivers/net/dsa/mt7530.h
 411 +++ b/drivers/net/dsa/mt7530.h
 412 @@ -391,47 +391,8 @@ enum mt7530_vlan_port_acc_frm {
 413                                          CCR_TX_OCT_CNT_BAD)
 414
 415  /* MT7531 SGMII register group */
 416 -#define MT7531_SGMII_REG_BASE          0x5000
 417 -#define MT7531_SGMII_REG(p, r)         (MT7531_SGMII_REG_BASE + \
 418 -                                       ((p) - 5) * 0x1000 + (r))
 419 -
 420 -/* Register forSGMII PCS_CONTROL_1 */
 421 -#define MT7531_PCS_CONTROL_1(p)                MT7531_SGMII_REG(p, 0x00)
 422 -#define  MT7531_SGMII_LINK_STATUS      BIT(18)
 423 -#define  MT7531_SGMII_AN_ENABLE                BIT(12)
 424 -#define  MT7531_SGMII_AN_RESTART       BIT(9)
 425 -#define  MT7531_SGMII_AN_COMPLETE      BIT(21)
 426 -
 427 -/* Register for SGMII PCS_SPPED_ABILITY */
 428 -#define MT7531_PCS_SPEED_ABILITY(p)    MT7531_SGMII_REG(p, 0x08)
 429 -#define  MT7531_SGMII_TX_CONFIG_MASK   GENMASK(15, 0)
 430 -#define  MT7531_SGMII_TX_CONFIG                BIT(0)
 431 -
 432 -/* Register for SGMII_MODE */
 433 -#define MT7531_SGMII_MODE(p)           MT7531_SGMII_REG(p, 0x20)
 434 -#define  MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
 435 -#define  MT7531_SGMII_IF_MODE_MASK     GENMASK(5, 1)
 436 -#define  MT7531_SGMII_FORCE_DUPLEX     BIT(4)
 437 -#define  MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
 438 -#define  MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
 439 -#define  MT7531_SGMII_FORCE_SPEED_100  BIT(2)
 440 -#define  MT7531_SGMII_FORCE_SPEED_10   0
 441 -#define  MT7531_SGMII_SPEED_DUPLEX_AN  BIT(1)
 442 -
 443 -enum mt7531_sgmii_force_duplex {
 444 -       MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
 445 -       MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
 446 -};
 447 -
 448 -/* Fields of QPHY_PWR_STATE_CTRL */
 449 -#define MT7531_QPHY_PWR_STATE_CTRL(p)  MT7531_SGMII_REG(p, 0xe8)
 450 -#define  MT7531_SGMII_PHYA_PWD         BIT(4)
 451 -
 452 -/* Values of SGMII SPEED */
 453 -#define MT7531_PHYA_CTRL_SIGNAL3(p)    MT7531_SGMII_REG(p, 0x128)
 454 -#define  MT7531_RG_TPHY_SPEED_MASK     (BIT(2) | BIT(3))
 455 -#define  MT7531_RG_TPHY_SPEED_1_25G    0x0
 456 -#define  MT7531_RG_TPHY_SPEED_3_125G   BIT(2)
 457 +#define MT7531_SGMII_REG_BASE(p)       (0x5000 + ((p) - 5) * 0x1000)
 458 +#define MT7531_PHYA_CTRL_SIGNAL3       0x128
 459
 460  /* Register for system reset */
 461  #define MT7530_SYS_CTRL                        0x7000
 462 @@ -730,13 +691,13 @@ struct mt7530_fdb {
 463   * @pm:                The matrix used to show all connections with the port.
 464   * @pvid:      The VLAN specified is to be considered a PVID at ingress.  Any
 465   *             untagged frames will be assigned to the related VLAN.
 466 - * @vlan_filtering: The flags indicating whether the port that can recognize
 467 - *                 VLAN-tagged frames.
 468 + * @sgmii_pcs: Pointer to PCS instance for SerDes ports
 469   */
 470  struct mt7530_port {
 471         bool enable;
 472         u32 pm;
 473         u16 pvid;
 474 +       struct phylink_pcs *sgmii_pcs;
 475  };
 476
 477  /* Port 5 interface select definitions */