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[openwrt/staging/stintel.git] / target / linux / generic / backport-6.1 / 750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
1 From 5d8d05fbf804b4485646d39551ac27452e45afd3 Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Tue, 25 Jul 2023 01:52:02 +0100
4 Subject: [PATCH 099/250] net: ethernet: mtk_eth_soc: add version in
5 mtk_soc_data
6
7 Introduce version field in mtk_soc_data data structure in order to
8 make mtk_eth driver easier to maintain for chipset configuration
9 codebase. Get rid of MTK_NETSYS_V2 bit in chip capabilities.
10 This is a preliminary patch to introduce support for MT7988 SoC.
11
12 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
13 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
14 Link: https://lore.kernel.org/r/e52fae302ca135436e5cdd26d38d87be2da63055.1690246066.git.daniel@makrotopia.org
15 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
16 ---
17 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 55 +++++++++++--------
18 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 36 +++++++-----
19 drivers/net/ethernet/mediatek/mtk_ppe.c | 18 +++---
20 .../net/ethernet/mediatek/mtk_ppe_offload.c | 2 +-
21 drivers/net/ethernet/mediatek/mtk_wed.c | 4 +-
22 5 files changed, 66 insertions(+), 49 deletions(-)
23
24 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
25 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
26 @@ -580,7 +580,7 @@ static void mtk_set_queue_speed(struct m
27 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
28 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
29 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
30 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
31 + if (mtk_is_netsys_v1(eth))
32 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
33
34 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
35 @@ -956,7 +956,7 @@ static bool mtk_rx_get_desc(struct mtk_e
36 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
37 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
38 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
39 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
40 + if (mtk_is_netsys_v2_or_greater(eth)) {
41 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
42 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
43 }
44 @@ -1014,7 +1014,7 @@ static int mtk_init_fq_dma(struct mtk_et
45
46 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
47 txd->txd4 = 0;
48 - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
49 + if (mtk_is_netsys_v2_or_greater(eth)) {
50 txd->txd5 = 0;
51 txd->txd6 = 0;
52 txd->txd7 = 0;
53 @@ -1205,7 +1205,7 @@ static void mtk_tx_set_dma_desc(struct n
54 struct mtk_mac *mac = netdev_priv(dev);
55 struct mtk_eth *eth = mac->hw;
56
57 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
58 + if (mtk_is_netsys_v2_or_greater(eth))
59 mtk_tx_set_dma_desc_v2(dev, txd, info);
60 else
61 mtk_tx_set_dma_desc_v1(dev, txd, info);
62 @@ -1512,7 +1512,7 @@ static void mtk_update_rx_cpu_idx(struct
63
64 static bool mtk_page_pool_enabled(struct mtk_eth *eth)
65 {
66 - return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2);
67 + return eth->soc->version == 2;
68 }
69
70 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
71 @@ -1854,7 +1854,7 @@ static int mtk_poll_rx(struct napi_struc
72 break;
73
74 /* find out which mac the packet come from. values start at 1 */
75 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
76 + if (mtk_is_netsys_v2_or_greater(eth))
77 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
78 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
79 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
80 @@ -1950,7 +1950,7 @@ static int mtk_poll_rx(struct napi_struc
81 skb->dev = netdev;
82 bytes += skb->len;
83
84 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
85 + if (mtk_is_netsys_v2_or_greater(eth)) {
86 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
87 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
88 if (hash != MTK_RXD5_FOE_ENTRY)
89 @@ -1975,8 +1975,8 @@ static int mtk_poll_rx(struct napi_struc
90 /* When using VLAN untagging in combination with DSA, the
91 * hardware treats the MTK special tag as a VLAN and untags it.
92 */
93 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
94 - (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) {
95 + if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) &&
96 + netdev_uses_dsa(netdev)) {
97 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
98
99 if (port < ARRAY_SIZE(eth->dsa_meta) &&
100 @@ -2286,7 +2286,7 @@ static int mtk_tx_alloc(struct mtk_eth *
101 txd->txd2 = next_ptr;
102 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
103 txd->txd4 = 0;
104 - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
105 + if (mtk_is_netsys_v2_or_greater(eth)) {
106 txd->txd5 = 0;
107 txd->txd6 = 0;
108 txd->txd7 = 0;
109 @@ -2339,14 +2339,14 @@ static int mtk_tx_alloc(struct mtk_eth *
110 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
111 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
112 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
113 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
114 + if (mtk_is_netsys_v1(eth))
115 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
116 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
117 ofs += MTK_QTX_OFFSET;
118 }
119 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16);
120 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
121 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
122 + if (mtk_is_netsys_v2_or_greater(eth))
123 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
124 } else {
125 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
126 @@ -2475,7 +2475,7 @@ static int mtk_rx_alloc(struct mtk_eth *
127
128 rxd->rxd3 = 0;
129 rxd->rxd4 = 0;
130 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
131 + if (mtk_is_netsys_v2_or_greater(eth)) {
132 rxd->rxd5 = 0;
133 rxd->rxd6 = 0;
134 rxd->rxd7 = 0;
135 @@ -3023,7 +3023,7 @@ static int mtk_start_dma(struct mtk_eth
136 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
137 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
138
139 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
140 + if (mtk_is_netsys_v2_or_greater(eth))
141 val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
142 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
143 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
144 @@ -3165,7 +3165,7 @@ static int mtk_open(struct net_device *d
145 phylink_start(mac->phylink);
146 netif_tx_start_all_queues(dev);
147
148 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
149 + if (mtk_is_netsys_v2_or_greater(eth))
150 return 0;
151
152 if (mtk_uses_dsa(dev) && !eth->prog) {
153 @@ -3430,7 +3430,7 @@ static void mtk_hw_reset(struct mtk_eth
154 {
155 u32 val;
156
157 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
158 + if (mtk_is_netsys_v2_or_greater(eth)) {
159 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
160 val = RSTCTRL_PPE0_V2;
161 } else {
162 @@ -3442,7 +3442,7 @@ static void mtk_hw_reset(struct mtk_eth
163
164 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
165
166 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
167 + if (mtk_is_netsys_v2_or_greater(eth))
168 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
169 0x3ffffff);
170 }
171 @@ -3468,7 +3468,7 @@ static void mtk_hw_warm_reset(struct mtk
172 return;
173 }
174
175 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
176 + if (mtk_is_netsys_v2_or_greater(eth))
177 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
178 else
179 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
180 @@ -3638,7 +3638,7 @@ static int mtk_hw_init(struct mtk_eth *e
181 else
182 mtk_hw_reset(eth);
183
184 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
185 + if (mtk_is_netsys_v2_or_greater(eth)) {
186 /* Set FE to PDMAv2 if necessary */
187 val = mtk_r32(eth, MTK_FE_GLO_MISC);
188 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
189 @@ -3675,7 +3675,7 @@ static int mtk_hw_init(struct mtk_eth *e
190 */
191 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
192 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
193 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
194 + if (mtk_is_netsys_v1(eth)) {
195 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
196 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
197
198 @@ -3697,7 +3697,7 @@ static int mtk_hw_init(struct mtk_eth *e
199 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
200 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
201
202 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
203 + if (mtk_is_netsys_v2_or_greater(eth)) {
204 /* PSE should not drop port8 and port9 packets from WDMA Tx */
205 mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
206
207 @@ -4486,7 +4486,7 @@ static int mtk_probe(struct platform_dev
208 }
209 }
210
211 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
212 + if (mtk_is_netsys_v2_or_greater(eth)) {
213 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
214 if (!res) {
215 err = -EINVAL;
216 @@ -4594,9 +4594,8 @@ static int mtk_probe(struct platform_dev
217 }
218
219 if (eth->soc->offload_version) {
220 - u32 num_ppe;
221 + u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1;
222
223 - num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
224 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
225 for (i = 0; i < num_ppe; i++) {
226 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
227 @@ -4688,6 +4687,7 @@ static const struct mtk_soc_data mt2701_
228 .hw_features = MTK_HW_FEATURES,
229 .required_clks = MT7623_CLKS_BITMAP,
230 .required_pctl = true,
231 + .version = 1,
232 .txrx = {
233 .txd_size = sizeof(struct mtk_tx_dma),
234 .rxd_size = sizeof(struct mtk_rx_dma),
235 @@ -4704,6 +4704,7 @@ static const struct mtk_soc_data mt7621_
236 .hw_features = MTK_HW_FEATURES,
237 .required_clks = MT7621_CLKS_BITMAP,
238 .required_pctl = false,
239 + .version = 1,
240 .offload_version = 1,
241 .hash_offset = 2,
242 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
243 @@ -4724,6 +4725,7 @@ static const struct mtk_soc_data mt7622_
244 .hw_features = MTK_HW_FEATURES,
245 .required_clks = MT7622_CLKS_BITMAP,
246 .required_pctl = false,
247 + .version = 1,
248 .offload_version = 2,
249 .hash_offset = 2,
250 .has_accounting = true,
251 @@ -4744,6 +4746,7 @@ static const struct mtk_soc_data mt7623_
252 .hw_features = MTK_HW_FEATURES,
253 .required_clks = MT7623_CLKS_BITMAP,
254 .required_pctl = true,
255 + .version = 1,
256 .offload_version = 1,
257 .hash_offset = 2,
258 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
259 @@ -4766,6 +4769,7 @@ static const struct mtk_soc_data mt7629_
260 .required_clks = MT7629_CLKS_BITMAP,
261 .required_pctl = false,
262 .has_accounting = true,
263 + .version = 1,
264 .txrx = {
265 .txd_size = sizeof(struct mtk_tx_dma),
266 .rxd_size = sizeof(struct mtk_rx_dma),
267 @@ -4783,6 +4787,7 @@ static const struct mtk_soc_data mt7981_
268 .hw_features = MTK_HW_FEATURES,
269 .required_clks = MT7981_CLKS_BITMAP,
270 .required_pctl = false,
271 + .version = 2,
272 .offload_version = 2,
273 .hash_offset = 4,
274 .has_accounting = true,
275 @@ -4804,6 +4809,7 @@ static const struct mtk_soc_data mt7986_
276 .hw_features = MTK_HW_FEATURES,
277 .required_clks = MT7986_CLKS_BITMAP,
278 .required_pctl = false,
279 + .version = 2,
280 .offload_version = 2,
281 .hash_offset = 4,
282 .has_accounting = true,
283 @@ -4824,6 +4830,7 @@ static const struct mtk_soc_data rt5350_
284 .hw_features = MTK_HW_FEATURES_MT7628,
285 .required_clks = MT7628_CLKS_BITMAP,
286 .required_pctl = false,
287 + .version = 1,
288 .txrx = {
289 .txd_size = sizeof(struct mtk_tx_dma),
290 .rxd_size = sizeof(struct mtk_rx_dma),
291 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
292 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
293 @@ -820,7 +820,6 @@ enum mkt_eth_capabilities {
294 MTK_SHARED_INT_BIT,
295 MTK_TRGMII_MT7621_CLK_BIT,
296 MTK_QDMA_BIT,
297 - MTK_NETSYS_V2_BIT,
298 MTK_SOC_MT7628_BIT,
299 MTK_RSTCTRL_PPE1_BIT,
300 MTK_U3_COPHY_V2_BIT,
301 @@ -855,7 +854,6 @@ enum mkt_eth_capabilities {
302 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
303 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
304 #define MTK_QDMA BIT(MTK_QDMA_BIT)
305 -#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
306 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
307 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
308 #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
309 @@ -934,11 +932,11 @@ enum mkt_eth_capabilities {
310 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
311 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
312 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
313 - MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
314 + MTK_RSTCTRL_PPE1)
315
316 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
317 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
318 - MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
319 + MTK_RSTCTRL_PPE1)
320
321 struct mtk_tx_dma_desc_info {
322 dma_addr_t addr;
323 @@ -1009,6 +1007,7 @@ struct mtk_reg_map {
324 * @required_pctl A bool value to show whether the SoC requires
325 * the extra setup for those pins used by GMAC.
326 * @hash_offset Flow table hash offset.
327 + * @version SoC version.
328 * @foe_entry_size Foe table entry size.
329 * @has_accounting Bool indicating support for accounting of
330 * offloaded flows.
331 @@ -1027,6 +1026,7 @@ struct mtk_soc_data {
332 bool required_pctl;
333 u8 offload_version;
334 u8 hash_offset;
335 + u8 version;
336 u16 foe_entry_size;
337 netdev_features_t hw_features;
338 bool has_accounting;
339 @@ -1183,6 +1183,16 @@ struct mtk_mac {
340 /* the struct describing the SoC. these are declared in the soc_xyz.c files */
341 extern const struct of_device_id of_mtk_match[];
342
343 +static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
344 +{
345 + return eth->soc->version == 1;
346 +}
347 +
348 +static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth)
349 +{
350 + return eth->soc->version > 1;
351 +}
352 +
353 static inline struct mtk_foe_entry *
354 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
355 {
356 @@ -1193,7 +1203,7 @@ mtk_foe_get_entry(struct mtk_ppe *ppe, u
357
358 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth)
359 {
360 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
361 + if (mtk_is_netsys_v2_or_greater(eth))
362 return MTK_FOE_IB1_BIND_TIMESTAMP_V2;
363
364 return MTK_FOE_IB1_BIND_TIMESTAMP;
365 @@ -1201,7 +1211,7 @@ static inline u32 mtk_get_ib1_ts_mask(st
366
367 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth)
368 {
369 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
370 + if (mtk_is_netsys_v2_or_greater(eth))
371 return MTK_FOE_IB1_BIND_PPPOE_V2;
372
373 return MTK_FOE_IB1_BIND_PPPOE;
374 @@ -1209,7 +1219,7 @@ static inline u32 mtk_get_ib1_ppoe_mask(
375
376 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth)
377 {
378 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
379 + if (mtk_is_netsys_v2_or_greater(eth))
380 return MTK_FOE_IB1_BIND_VLAN_TAG_V2;
381
382 return MTK_FOE_IB1_BIND_VLAN_TAG;
383 @@ -1217,7 +1227,7 @@ static inline u32 mtk_get_ib1_vlan_tag_m
384
385 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth)
386 {
387 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
388 + if (mtk_is_netsys_v2_or_greater(eth))
389 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2;
390
391 return MTK_FOE_IB1_BIND_VLAN_LAYER;
392 @@ -1225,7 +1235,7 @@ static inline u32 mtk_get_ib1_vlan_layer
393
394 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
395 {
396 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
397 + if (mtk_is_netsys_v2_or_greater(eth))
398 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
399
400 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
401 @@ -1233,7 +1243,7 @@ static inline u32 mtk_prep_ib1_vlan_laye
402
403 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
404 {
405 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
406 + if (mtk_is_netsys_v2_or_greater(eth))
407 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
408
409 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
410 @@ -1241,7 +1251,7 @@ static inline u32 mtk_get_ib1_vlan_layer
411
412 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth)
413 {
414 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
415 + if (mtk_is_netsys_v2_or_greater(eth))
416 return MTK_FOE_IB1_PACKET_TYPE_V2;
417
418 return MTK_FOE_IB1_PACKET_TYPE;
419 @@ -1249,7 +1259,7 @@ static inline u32 mtk_get_ib1_pkt_type_m
420
421 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val)
422 {
423 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
424 + if (mtk_is_netsys_v2_or_greater(eth))
425 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val);
426
427 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val);
428 @@ -1257,7 +1267,7 @@ static inline u32 mtk_get_ib1_pkt_type(s
429
430 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
431 {
432 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
433 + if (mtk_is_netsys_v2_or_greater(eth))
434 return MTK_FOE_IB2_MULTICAST_V2;
435
436 return MTK_FOE_IB2_MULTICAST;
437 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
438 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
439 @@ -207,7 +207,7 @@ int mtk_foe_entry_prepare(struct mtk_eth
440
441 memset(entry, 0, sizeof(*entry));
442
443 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
444 + if (mtk_is_netsys_v2_or_greater(eth)) {
445 val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |
446 FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE_V2, type) |
447 FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |
448 @@ -271,7 +271,7 @@ int mtk_foe_entry_set_pse_port(struct mt
449 u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
450 u32 val = *ib2;
451
452 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
453 + if (mtk_is_netsys_v2_or_greater(eth)) {
454 val &= ~MTK_FOE_IB2_DEST_PORT_V2;
455 val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT_V2, port);
456 } else {
457 @@ -422,7 +422,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
458 struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
459 u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
460
461 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
462 + if (mtk_is_netsys_v2_or_greater(eth)) {
463 *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
464 *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
465 MTK_FOE_IB2_WDMA_WINFO_V2;
466 @@ -446,7 +446,7 @@ int mtk_foe_entry_set_queue(struct mtk_e
467 {
468 u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
469
470 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
471 + if (mtk_is_netsys_v2_or_greater(eth)) {
472 *ib2 &= ~MTK_FOE_IB2_QID_V2;
473 *ib2 |= FIELD_PREP(MTK_FOE_IB2_QID_V2, queue);
474 *ib2 |= MTK_FOE_IB2_PSE_QOS_V2;
475 @@ -601,7 +601,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
476 struct mtk_foe_entry *hwe;
477 u32 val;
478
479 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
480 + if (mtk_is_netsys_v2_or_greater(eth)) {
481 entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2;
482 entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP_V2,
483 timestamp);
484 @@ -617,7 +617,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
485 hwe->ib1 = entry->ib1;
486
487 if (ppe->accounting) {
488 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
489 + if (mtk_is_netsys_v2_or_greater(eth))
490 val = MTK_FOE_IB2_MIB_CNT_V2;
491 else
492 val = MTK_FOE_IB2_MIB_CNT;
493 @@ -965,7 +965,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
494 MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
495 FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
496 MTK_PPE_ENTRIES_SHIFT);
497 - if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))
498 + if (mtk_is_netsys_v2_or_greater(ppe->eth))
499 val |= MTK_PPE_TB_CFG_INFO_SEL;
500 ppe_w32(ppe, MTK_PPE_TB_CFG, val);
501
502 @@ -981,7 +981,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
503 MTK_PPE_FLOW_CFG_IP4_NAPT |
504 MTK_PPE_FLOW_CFG_IP4_DSLITE |
505 MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;
506 - if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))
507 + if (mtk_is_netsys_v2_or_greater(ppe->eth))
508 val |= MTK_PPE_MD_TOAP_BYP_CRSN0 |
509 MTK_PPE_MD_TOAP_BYP_CRSN1 |
510 MTK_PPE_MD_TOAP_BYP_CRSN2 |
511 @@ -1023,7 +1023,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
512
513 ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
514
515 - if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) {
516 + if (mtk_is_netsys_v2_or_greater(ppe->eth)) {
517 ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
518 ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
519 }
520 --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
521 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
522 @@ -193,7 +193,7 @@ mtk_flow_set_output_device(struct mtk_et
523 if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {
524 mtk_foe_entry_set_wdma(eth, foe, info.wdma_idx, info.queue,
525 info.bss, info.wcid);
526 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
527 + if (mtk_is_netsys_v2_or_greater(eth)) {
528 switch (info.wdma_idx) {
529 case 0:
530 pse_port = 8;
531 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
532 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
533 @@ -1084,7 +1084,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
534 } else {
535 struct mtk_eth *eth = dev->hw->eth;
536
537 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
538 + if (mtk_is_netsys_v2_or_greater(eth))
539 wed_set(dev, MTK_WED_RESET_IDX,
540 MTK_WED_RESET_IDX_RX_V2);
541 else
542 @@ -1806,7 +1806,7 @@ void mtk_wed_add_hw(struct device_node *
543 hw->wdma = wdma;
544 hw->index = index;
545 hw->irq = irq;
546 - hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
547 + hw->version = mtk_is_netsys_v1(eth) ? 1 : 2;
548
549 if (hw->version == 1) {
550 hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
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