target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch

   1 From f5d43ddd334b7c32fcaed9ba46afbd85cb467f1f Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Sun, 19 Mar 2023 12:56:28 +0000
   4 Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for MT7981 SoC
   5
   6 The MediaTek MT7981 SoC comes with two 1G/2.5G SGMII ports, just like
   7 MT7986.
   8
   9 In addition MT7981 is equipped with a built-in 1000Base-T PHY which can
  10 be used with GMAC1.
  11
  12 As many MT7981 boards make use of inverting SGMII signal polarity, add
  13 new device-tree attribute 'mediatek,pn_swap' to support them.
  14
  15 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  16 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  17 ---
  18  drivers/net/ethernet/mediatek/mtk_eth_path.c | 14 +++++++--
  19  drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 21 +++++++++++++
  20  drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 31 ++++++++++++++++++++
  21  drivers/net/ethernet/mediatek/mtk_sgmii.c    | 10 +++++++
  22  4 files changed, 73 insertions(+), 3 deletions(-)
  23
  24 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
  25 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
  26 @@ -96,12 +96,20 @@ static int set_mux_gmac2_gmac0_to_gephy(
  27
  28  static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)
  29  {
  30 -       unsigned int val = 0;
  31 +       unsigned int val = 0, mask = 0, reg = 0;
  32         bool updated = true;
  33
  34         switch (path) {
  35         case MTK_ETH_PATH_GMAC2_SGMII:
  36 -               val = CO_QPHY_SEL;
  37 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) {
  38 +                       reg = USB_PHY_SWITCH_REG;
  39 +                       val = SGMII_QPHY_SEL;
  40 +                       mask = QPHY_SEL_MASK;
  41 +               } else {
  42 +                       reg = INFRA_MISC2;
  43 +                       val = CO_QPHY_SEL;
  44 +                       mask = val;
  45 +               }
  46                 break;
  47         default:
  48                 updated = false;
  49 @@ -109,7 +117,7 @@ static int set_mux_u3_gmac2_to_qphy(stru
  50         }
  51
  52         if (updated)
  53 -               regmap_update_bits(eth->infra, INFRA_MISC2, CO_QPHY_SEL, val);
  54 +               regmap_update_bits(eth->infra, reg, mask, val);
  55
  56         dev_dbg(eth->dev, "path %s in %s updated = %d\n",
  57                 mtk_eth_path_name(path), __func__, updated);
  58 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  59 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  60 @@ -4804,6 +4804,26 @@ static const struct mtk_soc_data mt7629_
  61         },
  62  };
  63
  64 +static const struct mtk_soc_data mt7981_data = {
  65 +       .reg_map = &mt7986_reg_map,
  66 +       .ana_rgc3 = 0x128,
  67 +       .caps = MT7981_CAPS,
  68 +       .hw_features = MTK_HW_FEATURES,
  69 +       .required_clks = MT7981_CLKS_BITMAP,
  70 +       .required_pctl = false,
  71 +       .offload_version = 2,
  72 +       .hash_offset = 4,
  73 +       .foe_entry_size = sizeof(struct mtk_foe_entry),
  74 +       .txrx = {
  75 +               .txd_size = sizeof(struct mtk_tx_dma_v2),
  76 +               .rxd_size = sizeof(struct mtk_rx_dma_v2),
  77 +               .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
  78 +               .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
  79 +               .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
  80 +               .dma_len_offset = 8,
  81 +       },
  82 +};
  83 +
  84  static const struct mtk_soc_data mt7986_data = {
  85         .reg_map = &mt7986_reg_map,
  86         .ana_rgc3 = 0x128,
  87 @@ -4846,6 +4866,7 @@ const struct of_device_id of_mtk_match[]
  88         { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
  89         { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
  90         { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
  91 +       { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
  92         { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
  93         { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
  94         {},
  95 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  96 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  97 @@ -556,11 +556,22 @@
  98  #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
  99  #define        SGMII_PHYA_PWD          BIT(4)
 100
 101 +/* Register to QPHY wrapper control */
 102 +#define SGMSYS_QPHY_WRAP_CTRL  0xec
 103 +#define SGMII_PN_SWAP_MASK     GENMASK(1, 0)
 104 +#define SGMII_PN_SWAP_TX_RX    (BIT(0) | BIT(1))
 105 +#define MTK_SGMII_FLAG_PN_SWAP BIT(0)
 106 +
 107  /* Infrasys subsystem config registers */
 108  #define INFRA_MISC2            0x70c
 109  #define CO_QPHY_SEL            BIT(0)
 110  #define GEPHY_MAC_SEL          BIT(1)
 111
 112 +/* Top misc registers */
 113 +#define USB_PHY_SWITCH_REG     0x218
 114 +#define QPHY_SEL_MASK          GENMASK(1, 0)
 115 +#define SGMII_QPHY_SEL         0x2
 116 +
 117  /* MT7628/88 specific stuff */
 118  #define MT7628_PDMA_OFFSET     0x0800
 119  #define MT7628_SDM_OFFSET      0x0c00
 120 @@ -741,6 +752,17 @@ enum mtk_clks_map {
 121                                  BIT(MTK_CLK_SGMII2_CDR_FB) | \
 122                                  BIT(MTK_CLK_SGMII_CK) | \
 123                                  BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
 124 +#define MT7981_CLKS_BITMAP     (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
 125 +                                BIT(MTK_CLK_WOCPU0) | \
 126 +                                BIT(MTK_CLK_SGMII_TX_250M) | \
 127 +                                BIT(MTK_CLK_SGMII_RX_250M) | \
 128 +                                BIT(MTK_CLK_SGMII_CDR_REF) | \
 129 +                                BIT(MTK_CLK_SGMII_CDR_FB) | \
 130 +                                BIT(MTK_CLK_SGMII2_TX_250M) | \
 131 +                                BIT(MTK_CLK_SGMII2_RX_250M) | \
 132 +                                BIT(MTK_CLK_SGMII2_CDR_REF) | \
 133 +                                BIT(MTK_CLK_SGMII2_CDR_FB) | \
 134 +                                BIT(MTK_CLK_SGMII_CK))
 135  #define MT7986_CLKS_BITMAP     (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
 136                                  BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
 137                                  BIT(MTK_CLK_SGMII_TX_250M) | \
 138 @@ -854,6 +876,7 @@ enum mkt_eth_capabilities {
 139         MTK_NETSYS_V2_BIT,
 140         MTK_SOC_MT7628_BIT,
 141         MTK_RSTCTRL_PPE1_BIT,
 142 +       MTK_U3_COPHY_V2_BIT,
 143
 144         /* MUX BITS*/
 145         MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
 146 @@ -888,6 +911,7 @@ enum mkt_eth_capabilities {
 147  #define MTK_NETSYS_V2          BIT(MTK_NETSYS_V2_BIT)
 148  #define MTK_SOC_MT7628         BIT(MTK_SOC_MT7628_BIT)
 149  #define MTK_RSTCTRL_PPE1       BIT(MTK_RSTCTRL_PPE1_BIT)
 150 +#define MTK_U3_COPHY_V2                BIT(MTK_U3_COPHY_V2_BIT)
 151
 152  #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW          \
 153         BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
 154 @@ -960,6 +984,11 @@ enum mkt_eth_capabilities {
 155                       MTK_MUX_U3_GMAC2_TO_QPHY | \
 156                       MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
 157
 158 +#define MT7981_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
 159 +                     MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
 160 +                     MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
 161 +                     MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
 162 +
 163  #define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
 164                       MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
 165                       MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
 166 @@ -1073,12 +1102,14 @@ struct mtk_soc_data {
 167   * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
 168   * @interface:         Currently configured interface mode
 169   * @pcs:               Phylink PCS structure
 170 + * @flags:             Flags indicating hardware properties
 171   */
 172  struct mtk_pcs {
 173         struct regmap   *regmap;
 174         u32             ana_rgc3;
 175         phy_interface_t interface;
 176         struct phylink_pcs pcs;
 177 +       u32             flags;
 178  };
 179
 180  /* struct mtk_sgmii -  This is the structure holding sgmii regmap and its
 181 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
 182 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
 183 @@ -87,6 +87,11 @@ static int mtk_pcs_config(struct phylink
 184                 regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
 185                                    SGMII_PHYA_PWD, SGMII_PHYA_PWD);
 186
 187 +               if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
 188 +                       regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
 189 +                                          SGMII_PN_SWAP_MASK,
 190 +                                          SGMII_PN_SWAP_TX_RX);
 191 +
 192                 /* Reset SGMII PCS state */
 193                 regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
 194                                    SGMII_SW_RESET, SGMII_SW_RESET);
 195 @@ -186,6 +191,11 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
 196
 197                 ss->pcs[i].ana_rgc3 = ana_rgc3;
 198                 ss->pcs[i].regmap = syscon_node_to_regmap(np);
 199 +
 200 +               ss->pcs[i].flags = 0;
 201 +               if (of_property_read_bool(np, "mediatek,pnswap"))
 202 +                       ss->pcs[i].flags |= MTK_SGMII_FLAG_PN_SWAP;
 203 +
 204                 of_node_put(np);
 205                 if (IS_ERR(ss->pcs[i].regmap))
 206                         return PTR_ERR(ss->pcs[i].regmap);