a0bb7fa888a718557ebf286e8c5b4fa620ec2588
[openwrt/staging/stintel.git] / target / linux / generic / backport-5.10 / 765-v5.15-net-dsa-mt7530-disable-learning-on-standalone-ports.patch
1 From ba2203f36b981235556504fb7b62baee28512a40 Mon Sep 17 00:00:00 2001
2 From: DENG Qingfang <dqfext@gmail.com>
3 Date: Tue, 24 Aug 2021 11:37:50 +0800
4 Subject: [PATCH] net: dsa: mt7530: disable learning on standalone ports
5
6 This is a partial backport of commit 5a30833b9a16f8d1aa15de06636f9317ca51f9df
7 ("net: dsa: mt7530: support MDB and bridge flag operations") upstream.
8
9 Make sure that the standalone ports start up with learning disabled.
10
11 Signed-off-by: DENG Qingfang <dqfext@gmail.com>
12 ---
13 drivers/net/dsa/mt7530.c | 16 ++++++++++++++--
14 1 file changed, 14 insertions(+), 2 deletions(-)
15
16 --- a/drivers/net/dsa/mt7530.c
17 +++ b/drivers/net/dsa/mt7530.c
18 @@ -1163,6 +1163,8 @@ mt7530_port_bridge_join(struct dsa_switc
19 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
20 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
21
22 + mt7530_clear(priv, MT7530_PSC_P(port), SA_DIS);
23 +
24 mutex_unlock(&priv->reg_mutex);
25
26 return 0;
27 @@ -1260,6 +1262,8 @@ mt7530_port_bridge_leave(struct dsa_swit
28 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
29 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
30
31 + mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
32 +
33 mutex_unlock(&priv->reg_mutex);
34 }
35
36 @@ -1817,9 +1821,13 @@ mt7530_setup(struct dsa_switch *ds)
37 ret = mt753x_cpu_port_enable(ds, i);
38 if (ret)
39 return ret;
40 - } else
41 + } else {
42 mt7530_port_disable(ds, i);
43
44 + /* Disable learning by default on all user ports */
45 + mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
46 + }
47 +
48 /* Enable consistent egress tag */
49 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
50 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
51 @@ -1979,9 +1987,13 @@ mt7531_setup(struct dsa_switch *ds)
52 ret = mt753x_cpu_port_enable(ds, i);
53 if (ret)
54 return ret;
55 - } else
56 + } else {
57 mt7530_port_disable(ds, i);
58
59 + /* Disable learning by default on all user ports */
60 + mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
61 + }
62 +
63 /* Enable consistent egress tag */
64 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
65 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));