1 /* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su) */
2 /* cache manipulation adapted from Broadcom code */
3 /* idea taken from original bunzip2 decompressor code */
4 /* Copyright 2004 Manuel Novoa III (mjn3@codepoet.org) */
5 /* Licensed under the linux kernel's version of the GPL.*/
8 #include <asm/regdef.h>
10 #define KSEG0 0x80000000
16 #define CONF1_DA_SHIFT 7 /* D$ associativity */
17 #define CONF1_DA_MASK 0x00000380
18 #define CONF1_DA_BASE 1
19 #define CONF1_DL_SHIFT 10 /* D$ line size */
20 #define CONF1_DL_MASK 0x00001c00
21 #define CONF1_DL_BASE 2
22 #define CONF1_DS_SHIFT 13 /* D$ sets/way */
23 #define CONF1_DS_MASK 0x0000e000
24 #define CONF1_DS_BASE 64
25 #define CONF1_IA_SHIFT 16 /* I$ associativity */
26 #define CONF1_IA_MASK 0x00070000
27 #define CONF1_IA_BASE 1
28 #define CONF1_IL_SHIFT 19 /* I$ line size */
29 #define CONF1_IL_MASK 0x00380000
30 #define CONF1_IL_BASE 2
31 #define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
32 #define CONF1_IS_MASK 0x01c00000
33 #define CONF1_IS_BASE 64
35 #define Index_Invalidate_I 0x00
36 #define Index_Writeback_Inv_D 0x01
48 /* Copy decompressor code to the right place */
61 /* At this point we need to invalidate dcache and */
62 /* icache before jumping to new code */
64 1: /* Get cache sizes */
76 sll s1,t0,s1 /* s1 has D$ cache line size */
81 addiu s2,CONF1_DA_BASE /* s2 now has D$ associativity */
87 sll s3,s3,t0 /* s3 has D$ sets per way */
89 multu s2,s3 /* sets/way * associativity */
90 mflo t0 /* total cache lines */
92 multu s1,t0 /* D$ linesize * lines */
93 mflo s2 /* s2 is now D$ size in bytes */
95 /* Initilize the D$: */
99 li t0,KSEG0 /* Just an address for the first $ line */
100 addu t1,t0,s2 /* + size of cache == end */
103 1: cache Index_Writeback_Inv_D,0(t0)
109 /* Now we get to do it all again for the I$ */
111 move s3,zero /* just in case there is no icache */
119 srl t0,CONF1_IL_SHIFT
121 sll s3,t0 /* s3 has I$ cache line size */
125 srl t0,CONF1_IA_SHIFT
126 addiu s4,t0,CONF1_IA_BASE /* s4 now has I$ associativity */
130 srl t0,CONF1_IS_SHIFT
132 sll s5,t0 /* s5 has I$ sets per way */
134 multu s4,s5 /* sets/way * associativity */
135 mflo t0 /* s4 is now total cache lines */
137 multu s3,t0 /* I$ linesize * lines */
138 mflo s4 /* s4 is cache size in bytes */
140 /* Initilize the I$: */
144 li t0,KSEG0 /* Just an address for the first $ line */
145 addu t1,t0,s4 /* + size of cache == end */
148 1: cache Index_Invalidate_I,0(t0)
154 move a0,s4 /* icache size */
155 move a1,s3 /* icache line size */
156 move a2,s2 /* dcache size */
158 move a3,s1 /* dcache line size */