target/linux/ath79/patches-5.15/316-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch

   1 From: Gabor Juhos <juhosg@openwrt.org>
   2 Subject: [PATCH] ar71xx: swizzle address for PCI byte/word access on AR71xx
   3
   4 Closes #11683.
   5
   6 SVN-Revision: 32639
   7 ---
   8  .../mips/include/asm/mach-ath79/mangle-port.h | 111 ++++++++++++++++++
   9  1 file changed, 111 insertions(+)
  10  create mode 100644 arch/mips/include/asm/mach-ath79/mangle-port.h
  11
  12 --- /dev/null
  13 +++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
  14 @@ -0,0 +1,37 @@
  15 +/*
  16 + *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
  17 + *
  18 + *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
  19 + *      Copyright (C) 2003, 2004 Ralf Baechle
  20 + *
  21 + *  This program is free software; you can redistribute it and/or modify it
  22 + *  under the terms of the GNU General Public License version 2 as published
  23 + *  by the Free Software Foundation.
  24 + */
  25 +
  26 +#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
  27 +#define __ASM_MACH_ATH79_MANGLE_PORT_H
  28 +
  29 +#ifdef CONFIG_PCI_AR71XX
  30 +extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
  31 +extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
  32 +#else
  33 +#define ath79_pci_swizzle_b(port) (port)
  34 +#define ath79_pci_swizzle_w(port) (port)
  35 +#endif
  36 +
  37 +#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port)
  38 +#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port)
  39 +#define __swizzle_addr_l(port) (port)
  40 +#define __swizzle_addr_q(port) (port)
  41 +
  42 +# define ioswabb(a, x)           (x)
  43 +# define __mem_ioswabb(a, x)     (x)
  44 +# define ioswabw(a, x)           (x)
  45 +# define __mem_ioswabw(a, x)     cpu_to_le16(x)
  46 +# define ioswabl(a, x)           (x)
  47 +# define __mem_ioswabl(a, x)     cpu_to_le32(x)
  48 +# define ioswabq(a, x)           (x)
  49 +# define __mem_ioswabq(a, x)     cpu_to_le64(x)
  50 +
  51 +#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
  52 --- a/arch/mips/pci/pci-ar71xx.c
  53 +++ b/arch/mips/pci/pci-ar71xx.c
  54 @@ -68,6 +68,45 @@ static const u32 ar71xx_pci_read_mask[8]
  55         0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
  56  };
  57
  58 +static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
  59 +static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
  60 +
  61 +static inline bool ar71xx_is_pci_addr(unsigned long port)
  62 +{
  63 +       unsigned long phys = CPHYSADDR(port);
  64 +
  65 +       return (phys >= AR71XX_PCI_MEM_BASE &&
  66 +               phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
  67 +}
  68 +
  69 +static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
  70 +{
  71 +       return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
  72 +}
  73 +
  74 +static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
  75 +{
  76 +       return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
  77 +}
  78 +
  79 +unsigned long ath79_pci_swizzle_b(unsigned long port)
  80 +{
  81 +       if (__ath79_pci_swizzle_b)
  82 +               return __ath79_pci_swizzle_b(port);
  83 +
  84 +       return port;
  85 +}
  86 +EXPORT_SYMBOL(ath79_pci_swizzle_b);
  87 +
  88 +unsigned long ath79_pci_swizzle_w(unsigned long port)
  89 +{
  90 +       if (__ath79_pci_swizzle_w)
  91 +               return __ath79_pci_swizzle_w(port);
  92 +
  93 +       return port;
  94 +}
  95 +EXPORT_SYMBOL(ath79_pci_swizzle_w);
  96 +
  97  static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
  98  {
  99         u32 t;
 100 @@ -275,6 +314,9 @@ static int ar71xx_pci_probe(struct platf
 101
 102         register_pci_controller(&apc->pci_ctrl);
 103
 104 +       __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
 105 +       __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
 106 +
 107         return 0;
 108  }
 109