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ath11k-firmware: Move from kvalo to new upstream repository
[openwrt/staging/stintel.git] / target / linux / ath25 / patches-5.15 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/atheros/Makefile
2 +++ b/drivers/net/ethernet/atheros/Makefile
3 @@ -9,3 +9,4 @@ obj-$(CONFIG_ATL2) += atlx/
4 obj-$(CONFIG_ATL1E) += atl1e/
5 obj-$(CONFIG_ATL1C) += atl1c/
6 obj-$(CONFIG_ALX) += alx/
7 +obj-$(CONFIG_NET_AR231X) += ar231x/
8 --- a/drivers/net/ethernet/atheros/Kconfig
9 +++ b/drivers/net/ethernet/atheros/Kconfig
10 @@ -6,7 +6,7 @@
11 config NET_VENDOR_ATHEROS
12 bool "Atheros devices"
13 default y
14 - depends on (PCI || ATH79)
15 + depends on (PCI || ATH25 || ATH79)
16 help
17 If you have a network (Ethernet) card belonging to this class, say Y.
18
19 @@ -88,4 +88,10 @@ config ALX
20 To compile this driver as a module, choose M here. The module
21 will be called alx.
22
23 +config NET_AR231X
24 + tristate "Atheros AR231X built-in Ethernet support"
25 + depends on ATH25
26 + help
27 + Support for the AR231x/531x ethernet controller
28 +
29 endif # NET_VENDOR_ATHEROS
30 --- /dev/null
31 +++ b/drivers/net/ethernet/atheros/ar231x/Makefile
32 @@ -0,0 +1 @@
33 +obj-$(CONFIG_NET_AR231X) += ar231x.o
34 --- /dev/null
35 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
36 @@ -0,0 +1,1117 @@
37 +/*
38 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
39 + *
40 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
41 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
42 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
43 + *
44 + * Thanks to Atheros for providing hardware and documentation
45 + * enabling me to write this driver.
46 + *
47 + * This program is free software; you can redistribute it and/or modify
48 + * it under the terms of the GNU General Public License as published by
49 + * the Free Software Foundation; either version 2 of the License, or
50 + * (at your option) any later version.
51 + *
52 + * Additional credits:
53 + * This code is taken from John Taylor's Sibyte driver and then
54 + * modified for the AR2313.
55 + */
56 +
57 +#include <linux/module.h>
58 +#include <linux/types.h>
59 +#include <linux/errno.h>
60 +#include <linux/ioport.h>
61 +#include <linux/netdevice.h>
62 +#include <linux/etherdevice.h>
63 +#include <linux/interrupt.h>
64 +#include <linux/skbuff.h>
65 +#include <linux/init.h>
66 +#include <linux/delay.h>
67 +#include <linux/mm.h>
68 +#include <linux/mii.h>
69 +#include <linux/phy.h>
70 +#include <linux/platform_device.h>
71 +#include <linux/io.h>
72 +
73 +#define AR2313_MTU 1692
74 +#define AR2313_PRIOS 1
75 +#define AR2313_QUEUES (2*AR2313_PRIOS)
76 +#define AR2313_DESCR_ENTRIES 64
77 +
78 +#ifndef min
79 +#define min(a, b) (((a) < (b)) ? (a) : (b))
80 +#endif
81 +
82 +#ifndef SMP_CACHE_BYTES
83 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
84 +#endif
85 +
86 +#define AR2313_MBOX_SET_BIT 0x8
87 +
88 +#include "ar231x.h"
89 +
90 +/**
91 + * New interrupt handler strategy:
92 + *
93 + * An old interrupt handler worked using the traditional method of
94 + * replacing an skbuff with a new one when a packet arrives. However
95 + * the rx rings do not need to contain a static number of buffer
96 + * descriptors, thus it makes sense to move the memory allocation out
97 + * of the main interrupt handler and do it in a bottom half handler
98 + * and only allocate new buffers when the number of buffers in the
99 + * ring is below a certain threshold. In order to avoid starving the
100 + * NIC under heavy load it is however necessary to force allocation
101 + * when hitting a minimum threshold. The strategy for alloction is as
102 + * follows:
103 + *
104 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
105 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
106 + * the buffers in the interrupt handler
107 + * RX_RING_THRES - maximum number of buffers in the rx ring
108 + *
109 + * One advantagous side effect of this allocation approach is that the
110 + * entire rx processing can be done without holding any spin lock
111 + * since the rx rings and registers are totally independent of the tx
112 + * ring and its registers. This of course includes the kmalloc's of
113 + * new skb's. Thus start_xmit can run in parallel with rx processing
114 + * and the memory allocation on SMP systems.
115 + *
116 + * Note that running the skb reallocation in a bottom half opens up
117 + * another can of races which needs to be handled properly. In
118 + * particular it can happen that the interrupt handler tries to run
119 + * the reallocation while the bottom half is either running on another
120 + * CPU or was interrupted on the same CPU. To get around this the
121 + * driver uses bitops to prevent the reallocation routines from being
122 + * reentered.
123 + *
124 + * TX handling can also be done without holding any spin lock, wheee
125 + * this is fun! since tx_csm is only written to by the interrupt
126 + * handler.
127 + */
128 +
129 +/**
130 + * Threshold values for RX buffer allocation - the low water marks for
131 + * when to start refilling the rings are set to 75% of the ring
132 + * sizes. It seems to make sense to refill the rings entirely from the
133 + * intrrupt handler once it gets below the panic threshold, that way
134 + * we don't risk that the refilling is moved to another CPU when the
135 + * one running the interrupt handler just got the slab code hot in its
136 + * cache.
137 + */
138 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
139 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
140 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
141 +#define CRC_LEN 4
142 +#define RX_OFFSET 2
143 +
144 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
145 +#define VLAN_HDR 4
146 +#else
147 +#define VLAN_HDR 0
148 +#endif
149 +
150 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
151 + RX_OFFSET)
152 +
153 +#ifdef MODULE
154 +MODULE_LICENSE("GPL");
155 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@nbd.name>");
156 +MODULE_DESCRIPTION("AR231x Ethernet driver");
157 +#endif
158 +
159 +/* prototypes */
160 +static void ar231x_halt(struct net_device *dev);
161 +static void rx_tasklet_func(unsigned long data);
162 +static void rx_tasklet_cleanup(struct net_device *dev);
163 +static void ar231x_multicast_list(struct net_device *dev);
164 +static void ar231x_tx_timeout(struct net_device *dev, unsigned int txqueue);
165 +
166 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
167 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
168 + u16 value);
169 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
170 +static int ar231x_mdiobus_probe(struct net_device *dev);
171 +static void ar231x_adjust_link(struct net_device *dev);
172 +
173 +#ifndef ERR
174 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
175 +#endif
176 +
177 +#ifdef CONFIG_NET_POLL_CONTROLLER
178 +static void
179 +ar231x_netpoll(struct net_device *dev)
180 +{
181 + unsigned long flags;
182 +
183 + local_irq_save(flags);
184 + ar231x_interrupt(dev->irq, dev);
185 + local_irq_restore(flags);
186 +}
187 +#endif
188 +
189 +static const struct net_device_ops ar231x_ops = {
190 + .ndo_open = ar231x_open,
191 + .ndo_stop = ar231x_close,
192 + .ndo_start_xmit = ar231x_start_xmit,
193 + .ndo_set_rx_mode = ar231x_multicast_list,
194 + .ndo_do_ioctl = ar231x_ioctl,
195 + .ndo_validate_addr = eth_validate_addr,
196 + .ndo_set_mac_address = eth_mac_addr,
197 + .ndo_tx_timeout = ar231x_tx_timeout,
198 +#ifdef CONFIG_NET_POLL_CONTROLLER
199 + .ndo_poll_controller = ar231x_netpoll,
200 +#endif
201 +};
202 +
203 +static int ar231x_probe(struct platform_device *pdev)
204 +{
205 + struct net_device *dev;
206 + struct ar231x_private *sp;
207 + struct resource *res;
208 + unsigned long ar_eth_base;
209 + char buf[64];
210 +
211 + dev = alloc_etherdev(sizeof(struct ar231x_private));
212 +
213 + if (dev == NULL) {
214 + printk(KERN_ERR
215 + "ar231x: Unable to allocate net_device structure!\n");
216 + return -ENOMEM;
217 + }
218 +
219 + platform_set_drvdata(pdev, dev);
220 +
221 + SET_NETDEV_DEV(dev, &pdev->dev);
222 +
223 + sp = netdev_priv(dev);
224 + sp->dev = dev;
225 + sp->pdev = pdev;
226 + sp->cfg = pdev->dev.platform_data;
227 +
228 + sprintf(buf, "eth%d_membase", pdev->id);
229 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
230 + if (!res)
231 + return -ENODEV;
232 +
233 + sp->link = 0;
234 + ar_eth_base = res->start;
235 +
236 + sprintf(buf, "eth%d_irq", pdev->id);
237 + dev->irq = platform_get_irq_byname(pdev, buf);
238 +
239 + spin_lock_init(&sp->lock);
240 +
241 + dev->features |= NETIF_F_HIGHDMA;
242 + dev->netdev_ops = &ar231x_ops;
243 +
244 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long)dev);
245 + tasklet_disable(&sp->rx_tasklet);
246 +
247 + sp->eth_regs = ioremap(ar_eth_base, sizeof(*sp->eth_regs));
248 + if (!sp->eth_regs) {
249 + printk("Can't remap eth registers\n");
250 + return -ENXIO;
251 + }
252 +
253 + /**
254 + * When there's only one MAC, PHY regs are typically on ENET0,
255 + * even though the MAC might be on ENET1.
256 + * So remap PHY regs separately.
257 + */
258 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii");
259 + if (!res) {
260 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
261 + "eth1_mii");
262 + if (!res)
263 + return -ENODEV;
264 + }
265 + sp->phy_regs = ioremap(res->start, resource_size(res));
266 + if (!sp->phy_regs) {
267 + printk("Can't remap phy registers\n");
268 + return -ENXIO;
269 + }
270 +
271 + sp->dma_regs = ioremap(ar_eth_base + 0x1000,
272 + sizeof(*sp->dma_regs));
273 + if (!sp->dma_regs) {
274 + printk("Can't remap DMA registers\n");
275 + return -ENXIO;
276 + }
277 + dev->base_addr = ar_eth_base + 0x1000;
278 +
279 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
280 + sp->name[sizeof(sp->name) - 1] = '\0';
281 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
282 +
283 + if (ar231x_init(dev)) {
284 + /* ar231x_init() calls ar231x_init_cleanup() on error */
285 + kfree(dev);
286 + return -ENODEV;
287 + }
288 +
289 + if (register_netdev(dev)) {
290 + printk("%s: register_netdev failed\n", __func__);
291 + return -1;
292 + }
293 +
294 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
295 + dev->irq);
296 +
297 + sp->mii_bus = mdiobus_alloc();
298 + if (sp->mii_bus == NULL)
299 + return -1;
300 +
301 + sp->mii_bus->priv = dev;
302 + sp->mii_bus->read = ar231x_mdiobus_read;
303 + sp->mii_bus->write = ar231x_mdiobus_write;
304 + sp->mii_bus->reset = ar231x_mdiobus_reset;
305 + sp->mii_bus->name = "ar231x_eth_mii";
306 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
307 +
308 + mdiobus_register(sp->mii_bus);
309 +
310 + if (ar231x_mdiobus_probe(dev) != 0) {
311 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
312 + rx_tasklet_cleanup(dev);
313 + ar231x_init_cleanup(dev);
314 + unregister_netdev(dev);
315 + kfree(dev);
316 + return -ENODEV;
317 + }
318 +
319 + return 0;
320 +}
321 +
322 +static void ar231x_multicast_list(struct net_device *dev)
323 +{
324 + struct ar231x_private *sp = netdev_priv(dev);
325 + unsigned int filter;
326 +
327 + filter = sp->eth_regs->mac_control;
328 +
329 + if (dev->flags & IFF_PROMISC)
330 + filter |= MAC_CONTROL_PR;
331 + else
332 + filter &= ~MAC_CONTROL_PR;
333 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
334 + filter |= MAC_CONTROL_PM;
335 + else
336 + filter &= ~MAC_CONTROL_PM;
337 +
338 + sp->eth_regs->mac_control = filter;
339 +}
340 +
341 +static void rx_tasklet_cleanup(struct net_device *dev)
342 +{
343 + struct ar231x_private *sp = netdev_priv(dev);
344 +
345 + /**
346 + * Tasklet may be scheduled. Need to get it removed from the list
347 + * since we're about to free the struct.
348 + */
349 +
350 + sp->unloading = 1;
351 + tasklet_enable(&sp->rx_tasklet);
352 + tasklet_kill(&sp->rx_tasklet);
353 +}
354 +
355 +static int ar231x_remove(struct platform_device *pdev)
356 +{
357 + struct net_device *dev = platform_get_drvdata(pdev);
358 + struct ar231x_private *sp = netdev_priv(dev);
359 +
360 + rx_tasklet_cleanup(dev);
361 + ar231x_init_cleanup(dev);
362 + unregister_netdev(dev);
363 + mdiobus_unregister(sp->mii_bus);
364 + mdiobus_free(sp->mii_bus);
365 + kfree(dev);
366 + return 0;
367 +}
368 +
369 +/**
370 + * Restart the AR2313 ethernet controller.
371 + */
372 +static int ar231x_restart(struct net_device *dev)
373 +{
374 + /* disable interrupts */
375 + disable_irq(dev->irq);
376 +
377 + /* stop mac */
378 + ar231x_halt(dev);
379 +
380 + /* initialize */
381 + ar231x_init(dev);
382 +
383 + /* enable interrupts */
384 + enable_irq(dev->irq);
385 +
386 + return 0;
387 +}
388 +
389 +static struct platform_driver ar231x_driver = {
390 + .driver.name = "ar231x-eth",
391 + .probe = ar231x_probe,
392 + .remove = ar231x_remove,
393 +};
394 +
395 +module_platform_driver(ar231x_driver);
396 +
397 +static void ar231x_free_descriptors(struct net_device *dev)
398 +{
399 + struct ar231x_private *sp = netdev_priv(dev);
400 +
401 + if (sp->rx_ring != NULL) {
402 + kfree((void *)KSEG0ADDR(sp->rx_ring));
403 + sp->rx_ring = NULL;
404 + sp->tx_ring = NULL;
405 + }
406 +}
407 +
408 +static int ar231x_allocate_descriptors(struct net_device *dev)
409 +{
410 + struct ar231x_private *sp = netdev_priv(dev);
411 + int size;
412 + int j;
413 + ar231x_descr_t *space;
414 +
415 + if (sp->rx_ring != NULL) {
416 + printk("%s: already done.\n", __func__);
417 + return 0;
418 + }
419 +
420 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
421 + space = kmalloc(size, GFP_KERNEL);
422 + if (space == NULL)
423 + return 1;
424 +
425 + /* invalidate caches */
426 + dma_cache_inv((unsigned int)space, size);
427 +
428 + /* now convert pointer to KSEG1 */
429 + space = (ar231x_descr_t *)KSEG1ADDR(space);
430 +
431 + memset((void *)space, 0, size);
432 +
433 + sp->rx_ring = space;
434 + space += AR2313_DESCR_ENTRIES;
435 +
436 + sp->tx_ring = space;
437 + space += AR2313_DESCR_ENTRIES;
438 +
439 + /* Initialize the transmit Descriptors */
440 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
441 + ar231x_descr_t *td = &sp->tx_ring[j];
442 +
443 + td->status = 0;
444 + td->devcs = DMA_TX1_CHAINED;
445 + td->addr = 0;
446 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
447 + }
448 +
449 + return 0;
450 +}
451 +
452 +/**
453 + * Generic cleanup handling data allocated during init. Used when the
454 + * module is unloaded or if an error occurs during initialization
455 + */
456 +static void ar231x_init_cleanup(struct net_device *dev)
457 +{
458 + struct ar231x_private *sp = netdev_priv(dev);
459 + struct sk_buff *skb;
460 + int j;
461 +
462 + ar231x_free_descriptors(dev);
463 +
464 + if (sp->eth_regs)
465 + iounmap((void *)sp->eth_regs);
466 + if (sp->dma_regs)
467 + iounmap((void *)sp->dma_regs);
468 + if (sp->phy_regs)
469 + iounmap((void *)sp->phy_regs);
470 +
471 + if (sp->rx_skb) {
472 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
473 + skb = sp->rx_skb[j];
474 + if (skb) {
475 + sp->rx_skb[j] = NULL;
476 + dev_kfree_skb(skb);
477 + }
478 + }
479 + kfree(sp->rx_skb);
480 + sp->rx_skb = NULL;
481 + }
482 +
483 + if (sp->tx_skb) {
484 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
485 + skb = sp->tx_skb[j];
486 + if (skb) {
487 + sp->tx_skb[j] = NULL;
488 + dev_kfree_skb(skb);
489 + }
490 + }
491 + kfree(sp->tx_skb);
492 + sp->tx_skb = NULL;
493 + }
494 +}
495 +
496 +static int ar231x_reset_reg(struct net_device *dev)
497 +{
498 + struct ar231x_private *sp = netdev_priv(dev);
499 + unsigned int ethsal, ethsah;
500 + unsigned int flags;
501 +
502 + sp->cfg->reset_set(sp->cfg->reset_mac);
503 + mdelay(10);
504 + sp->cfg->reset_clear(sp->cfg->reset_mac);
505 + mdelay(10);
506 + sp->cfg->reset_set(sp->cfg->reset_phy);
507 + mdelay(10);
508 + sp->cfg->reset_clear(sp->cfg->reset_phy);
509 + mdelay(10);
510 +
511 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
512 + mdelay(10);
513 + sp->dma_regs->bus_mode =
514 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
515 +
516 + /* enable interrupts */
517 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
518 + DMA_STATUS_RI | DMA_STATUS_TI |
519 + DMA_STATUS_FBE;
520 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
521 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
522 + sp->dma_regs->control =
523 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
524 +
525 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
526 + sp->eth_regs->vlan_tag = (0x8100);
527 +
528 + /* Enable Ethernet Interface */
529 + flags = (MAC_CONTROL_TE | /* transmit enable */
530 + MAC_CONTROL_PM | /* pass mcast */
531 + MAC_CONTROL_F | /* full duplex */
532 + MAC_CONTROL_HBD); /* heart beat disabled */
533 +
534 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
535 + flags |= MAC_CONTROL_PR;
536 + }
537 + sp->eth_regs->mac_control = flags;
538 +
539 + /* Set all Ethernet station address registers to their initial values */
540 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
541 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
542 +
543 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
544 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
545 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
546 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
547 +
548 + sp->eth_regs->mac_addr[0] = ethsah;
549 + sp->eth_regs->mac_addr[1] = ethsal;
550 +
551 + mdelay(10);
552 +
553 + return 0;
554 +}
555 +
556 +static int ar231x_init(struct net_device *dev)
557 +{
558 + struct ar231x_private *sp = netdev_priv(dev);
559 + int ecode = 0;
560 +
561 + /* Allocate descriptors */
562 + if (ar231x_allocate_descriptors(dev)) {
563 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
564 + dev->name, __func__);
565 + ecode = -EAGAIN;
566 + goto init_error;
567 + }
568 +
569 + /* Get the memory for the skb rings */
570 + if (sp->rx_skb == NULL) {
571 + sp->rx_skb =
572 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
573 + GFP_KERNEL);
574 + if (!(sp->rx_skb)) {
575 + printk("%s: %s: rx_skb kmalloc failed\n",
576 + dev->name, __func__);
577 + ecode = -EAGAIN;
578 + goto init_error;
579 + }
580 + }
581 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
582 +
583 + if (sp->tx_skb == NULL) {
584 + sp->tx_skb =
585 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
586 + GFP_KERNEL);
587 + if (!(sp->tx_skb)) {
588 + printk("%s: %s: tx_skb kmalloc failed\n",
589 + dev->name, __func__);
590 + ecode = -EAGAIN;
591 + goto init_error;
592 + }
593 + }
594 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
595 +
596 + /**
597 + * Set tx_csm before we start receiving interrupts, otherwise
598 + * the interrupt handler might think it is supposed to process
599 + * tx ints before we are up and running, which may cause a null
600 + * pointer access in the int handler.
601 + */
602 + sp->rx_skbprd = 0;
603 + sp->cur_rx = 0;
604 + sp->tx_prd = 0;
605 + sp->tx_csm = 0;
606 +
607 + /* Zero the stats before starting the interface */
608 + memset(&dev->stats, 0, sizeof(dev->stats));
609 +
610 + /**
611 + * We load the ring here as there seem to be no way to tell the
612 + * firmware to wipe the ring without re-initializing it.
613 + */
614 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
615 +
616 + /* Init hardware */
617 + ar231x_reset_reg(dev);
618 +
619 + /* Get the IRQ */
620 + ecode = request_irq(dev->irq, &ar231x_interrupt, 0,
621 + dev->name, dev);
622 + if (ecode) {
623 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
624 + dev->name, __func__, dev->irq);
625 + goto init_error;
626 + }
627 +
628 + tasklet_enable(&sp->rx_tasklet);
629 +
630 + return 0;
631 +
632 +init_error:
633 + ar231x_init_cleanup(dev);
634 + return ecode;
635 +}
636 +
637 +/**
638 + * Load the rx ring.
639 + *
640 + * Loading rings is safe without holding the spin lock since this is
641 + * done only before the device is enabled, thus no interrupts are
642 + * generated and by the interrupt handler/tasklet handler.
643 + */
644 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
645 +{
646 + struct ar231x_private *sp = netdev_priv(dev);
647 + short i, idx;
648 +
649 + idx = sp->rx_skbprd;
650 +
651 + for (i = 0; i < nr_bufs; i++) {
652 + struct sk_buff *skb;
653 + ar231x_descr_t *rd;
654 +
655 + if (sp->rx_skb[idx])
656 + break;
657 +
658 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
659 + if (!skb) {
660 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
661 + __func__);
662 + break;
663 + }
664 +
665 + /* Make sure IP header starts on a fresh cache line */
666 + skb->dev = dev;
667 + sp->rx_skb[idx] = skb;
668 +
669 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
670 +
671 + /* initialize dma descriptor */
672 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
673 + DMA_RX1_CHAINED);
674 + rd->addr = virt_to_phys(skb->data);
675 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
676 + rd->status = DMA_RX_OWN;
677 +
678 + idx = DSC_NEXT(idx);
679 + }
680 +
681 + if (i)
682 + sp->rx_skbprd = idx;
683 +}
684 +
685 +#define AR2313_MAX_PKTS_PER_CALL 64
686 +
687 +static int ar231x_rx_int(struct net_device *dev)
688 +{
689 + struct ar231x_private *sp = netdev_priv(dev);
690 + struct sk_buff *skb, *skb_new;
691 + ar231x_descr_t *rxdesc;
692 + unsigned int status;
693 + u32 idx;
694 + int pkts = 0;
695 + int rval;
696 +
697 + idx = sp->cur_rx;
698 +
699 + /* process at most the entire ring and then wait for another int */
700 + while (1) {
701 + rxdesc = &sp->rx_ring[idx];
702 + status = rxdesc->status;
703 +
704 + if (status & DMA_RX_OWN) {
705 + /* SiByte owns descriptor or descr not yet filled in */
706 + rval = 0;
707 + break;
708 + }
709 +
710 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
711 + rval = 1;
712 + break;
713 + }
714 +
715 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
716 + dev->stats.rx_errors++;
717 + dev->stats.rx_dropped++;
718 +
719 + /* add statistics counters */
720 + if (status & DMA_RX_ERR_CRC)
721 + dev->stats.rx_crc_errors++;
722 + if (status & DMA_RX_ERR_COL)
723 + dev->stats.rx_over_errors++;
724 + if (status & DMA_RX_ERR_LENGTH)
725 + dev->stats.rx_length_errors++;
726 + if (status & DMA_RX_ERR_RUNT)
727 + dev->stats.rx_over_errors++;
728 + if (status & DMA_RX_ERR_DESC)
729 + dev->stats.rx_over_errors++;
730 +
731 + } else {
732 + /* alloc new buffer. */
733 + skb_new = netdev_alloc_skb_ip_align(dev,
734 + AR2313_BUFSIZE);
735 + if (skb_new != NULL) {
736 + skb = sp->rx_skb[idx];
737 + /* set skb */
738 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
739 + 0x3fff) - CRC_LEN);
740 +
741 + dev->stats.rx_bytes += skb->len;
742 + skb->protocol = eth_type_trans(skb, dev);
743 + /* pass the packet to upper layers */
744 + netif_rx(skb);
745 +
746 + skb_new->dev = dev;
747 + /* reset descriptor's curr_addr */
748 + rxdesc->addr = virt_to_phys(skb_new->data);
749 +
750 + dev->stats.rx_packets++;
751 + sp->rx_skb[idx] = skb_new;
752 + } else {
753 + dev->stats.rx_dropped++;
754 + }
755 + }
756 +
757 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
758 + DMA_RX1_CHAINED);
759 + rxdesc->status = DMA_RX_OWN;
760 +
761 + idx = DSC_NEXT(idx);
762 + }
763 +
764 + sp->cur_rx = idx;
765 +
766 + return rval;
767 +}
768 +
769 +static void ar231x_tx_int(struct net_device *dev)
770 +{
771 + struct ar231x_private *sp = netdev_priv(dev);
772 + u32 idx;
773 + struct sk_buff *skb;
774 + ar231x_descr_t *txdesc;
775 + unsigned int status = 0;
776 +
777 + idx = sp->tx_csm;
778 +
779 + while (idx != sp->tx_prd) {
780 + txdesc = &sp->tx_ring[idx];
781 + status = txdesc->status;
782 +
783 + if (status & DMA_TX_OWN) {
784 + /* ar231x dma still owns descr */
785 + break;
786 + }
787 + /* done with this descriptor */
788 + dma_unmap_single(&sp->pdev->dev, txdesc->addr,
789 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
790 + DMA_TO_DEVICE);
791 + txdesc->status = 0;
792 +
793 + if (status & DMA_TX_ERROR) {
794 + dev->stats.tx_errors++;
795 + dev->stats.tx_dropped++;
796 + if (status & DMA_TX_ERR_UNDER)
797 + dev->stats.tx_fifo_errors++;
798 + if (status & DMA_TX_ERR_HB)
799 + dev->stats.tx_heartbeat_errors++;
800 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
801 + dev->stats.tx_carrier_errors++;
802 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
803 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
804 + dev->stats.tx_aborted_errors++;
805 + } else {
806 + /* transmit OK */
807 + dev->stats.tx_packets++;
808 + }
809 +
810 + skb = sp->tx_skb[idx];
811 + sp->tx_skb[idx] = NULL;
812 + idx = DSC_NEXT(idx);
813 + dev->stats.tx_bytes += skb->len;
814 + dev_kfree_skb_irq(skb);
815 + }
816 +
817 + sp->tx_csm = idx;
818 +}
819 +
820 +static void rx_tasklet_func(unsigned long data)
821 +{
822 + struct net_device *dev = (struct net_device *)data;
823 + struct ar231x_private *sp = netdev_priv(dev);
824 +
825 + if (sp->unloading)
826 + return;
827 +
828 + if (ar231x_rx_int(dev)) {
829 + tasklet_hi_schedule(&sp->rx_tasklet);
830 + } else {
831 + unsigned long flags;
832 +
833 + spin_lock_irqsave(&sp->lock, flags);
834 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
835 + spin_unlock_irqrestore(&sp->lock, flags);
836 + }
837 +}
838 +
839 +static void rx_schedule(struct net_device *dev)
840 +{
841 + struct ar231x_private *sp = netdev_priv(dev);
842 +
843 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
844 +
845 + tasklet_hi_schedule(&sp->rx_tasklet);
846 +}
847 +
848 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
849 +{
850 + struct net_device *dev = (struct net_device *)dev_id;
851 + struct ar231x_private *sp = netdev_priv(dev);
852 + unsigned int status, enabled;
853 +
854 + /* clear interrupt */
855 + /* Don't clear RI bit if currently disabled */
856 + status = sp->dma_regs->status;
857 + enabled = sp->dma_regs->intr_ena;
858 + sp->dma_regs->status = status & enabled;
859 +
860 + if (status & DMA_STATUS_NIS) {
861 + /* normal status */
862 + /**
863 + * Don't schedule rx processing if interrupt
864 + * is already disabled.
865 + */
866 + if (status & enabled & DMA_STATUS_RI) {
867 + /* receive interrupt */
868 + rx_schedule(dev);
869 + }
870 + if (status & DMA_STATUS_TI) {
871 + /* transmit interrupt */
872 + ar231x_tx_int(dev);
873 + }
874 + }
875 +
876 + /* abnormal status */
877 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
878 + ar231x_restart(dev);
879 +
880 + return IRQ_HANDLED;
881 +}
882 +
883 +static int ar231x_open(struct net_device *dev)
884 +{
885 + struct ar231x_private *sp = netdev_priv(dev);
886 + unsigned int ethsal, ethsah;
887 +
888 + /* reset the hardware, in case the MAC address changed */
889 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
890 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
891 +
892 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
893 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
894 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
895 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
896 +
897 + sp->eth_regs->mac_addr[0] = ethsah;
898 + sp->eth_regs->mac_addr[1] = ethsal;
899 +
900 + mdelay(10);
901 +
902 + dev->mtu = 1500;
903 + netif_start_queue(dev);
904 +
905 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
906 +
907 + phy_start(sp->phy_dev);
908 +
909 + return 0;
910 +}
911 +
912 +static void ar231x_tx_timeout(struct net_device *dev, unsigned int txqueue)
913 +{
914 + struct ar231x_private *sp = netdev_priv(dev);
915 + unsigned long flags;
916 +
917 + spin_lock_irqsave(&sp->lock, flags);
918 + ar231x_restart(dev);
919 + spin_unlock_irqrestore(&sp->lock, flags);
920 +}
921 +
922 +static void ar231x_halt(struct net_device *dev)
923 +{
924 + struct ar231x_private *sp = netdev_priv(dev);
925 + int j;
926 +
927 + tasklet_disable(&sp->rx_tasklet);
928 +
929 + /* kill the MAC */
930 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
931 + MAC_CONTROL_TE); /* disable Transmits */
932 + /* stop dma */
933 + sp->dma_regs->control = 0;
934 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
935 +
936 + /* place phy and MAC in reset */
937 + sp->cfg->reset_set(sp->cfg->reset_mac);
938 + sp->cfg->reset_set(sp->cfg->reset_phy);
939 +
940 + /* free buffers on tx ring */
941 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
942 + struct sk_buff *skb;
943 + ar231x_descr_t *txdesc;
944 +
945 + txdesc = &sp->tx_ring[j];
946 + txdesc->descr = 0;
947 +
948 + skb = sp->tx_skb[j];
949 + if (skb) {
950 + dev_kfree_skb(skb);
951 + sp->tx_skb[j] = NULL;
952 + }
953 + }
954 +}
955 +
956 +/**
957 + * close should do nothing. Here's why. It's called when
958 + * 'ifconfig bond0 down' is run. If it calls free_irq then
959 + * the irq is gone forever ! When bond0 is made 'up' again,
960 + * the ar231x_open () does not call request_irq (). Worse,
961 + * the call to ar231x_halt() generates a WDOG reset due to
962 + * the write to reset register and the box reboots.
963 + * Commenting this out is good since it allows the
964 + * system to resume when bond0 is made up again.
965 + */
966 +static int ar231x_close(struct net_device *dev)
967 +{
968 + struct ar231x_private *sp = netdev_priv(dev);
969 +#if 0
970 + /* Disable interrupts */
971 + disable_irq(dev->irq);
972 +
973 + /**
974 + * Without (or before) releasing irq and stopping hardware, this
975 + * is an absolute non-sense, by the way. It will be reset instantly
976 + * by the first irq.
977 + */
978 + netif_stop_queue(dev);
979 +
980 + /* stop the MAC and DMA engines */
981 + ar231x_halt(dev);
982 +
983 + /* release the interrupt */
984 + free_irq(dev->irq, dev);
985 +
986 +#endif
987 +
988 + phy_stop(sp->phy_dev);
989 +
990 + return 0;
991 +}
992 +
993 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
994 +{
995 + struct ar231x_private *sp = netdev_priv(dev);
996 + ar231x_descr_t *td;
997 + u32 idx;
998 +
999 + idx = sp->tx_prd;
1000 + td = &sp->tx_ring[idx];
1001 +
1002 + if (td->status & DMA_TX_OWN) {
1003 + /* free skbuf and lie to the caller that we sent it out */
1004 + dev->stats.tx_dropped++;
1005 + dev_kfree_skb(skb);
1006 +
1007 + /* restart transmitter in case locked */
1008 + sp->dma_regs->xmt_poll = 0;
1009 + return 0;
1010 + }
1011 +
1012 + /* Setup the transmit descriptor. */
1013 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1014 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1015 + td->addr = dma_map_single(&sp->pdev->dev, skb->data, skb->len, DMA_TO_DEVICE);
1016 + td->status = DMA_TX_OWN;
1017 +
1018 + /* kick transmitter last */
1019 + sp->dma_regs->xmt_poll = 0;
1020 +
1021 + sp->tx_skb[idx] = skb;
1022 + idx = DSC_NEXT(idx);
1023 + sp->tx_prd = idx;
1024 +
1025 + return 0;
1026 +}
1027 +
1028 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1029 +{
1030 + struct ar231x_private *sp = netdev_priv(dev);
1031 +
1032 + switch (cmd) {
1033 + case SIOCGMIIPHY:
1034 + case SIOCGMIIREG:
1035 + case SIOCSMIIREG:
1036 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1037 +
1038 + default:
1039 + break;
1040 + }
1041 +
1042 + return -EOPNOTSUPP;
1043 +}
1044 +
1045 +static void ar231x_adjust_link(struct net_device *dev)
1046 +{
1047 + struct ar231x_private *sp = netdev_priv(dev);
1048 + struct phy_device *phydev = sp->phy_dev;
1049 + u32 mc;
1050 +
1051 + if (!phydev->link) {
1052 + if (sp->link) {
1053 + pr_info("%s: link down\n", dev->name);
1054 + sp->link = 0;
1055 + }
1056 + return;
1057 + }
1058 + sp->link = 1;
1059 +
1060 + pr_info("%s: link up (%uMbps/%s duplex)\n", dev->name,
1061 + phydev->speed, phydev->duplex ? "full" : "half");
1062 +
1063 + mc = sp->eth_regs->mac_control;
1064 + if (phydev->duplex)
1065 + mc = (mc | MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
1066 + else
1067 + mc = (mc | MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
1068 + sp->eth_regs->mac_control = mc;
1069 + sp->duplex = phydev->duplex;
1070 +}
1071 +
1072 +#define MII_ADDR(phy, reg) \
1073 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1074 +
1075 +static int
1076 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1077 +{
1078 + struct net_device *const dev = bus->priv;
1079 + struct ar231x_private *sp = netdev_priv(dev);
1080 + volatile MII *ethernet = sp->phy_regs;
1081 +
1082 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1083 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1084 + ;
1085 + return ethernet->mii_data >> MII_DATA_SHIFT;
1086 +}
1087 +
1088 +static int
1089 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1090 +{
1091 + struct net_device *const dev = bus->priv;
1092 + struct ar231x_private *sp = netdev_priv(dev);
1093 + volatile MII *ethernet = sp->phy_regs;
1094 +
1095 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1096 + ;
1097 + ethernet->mii_data = value << MII_DATA_SHIFT;
1098 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1099 +
1100 + return 0;
1101 +}
1102 +
1103 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1104 +{
1105 + struct net_device *const dev = bus->priv;
1106 +
1107 + ar231x_reset_reg(dev);
1108 +
1109 + return 0;
1110 +}
1111 +
1112 +static int ar231x_mdiobus_probe(struct net_device *dev)
1113 +{
1114 + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1115 + struct ar231x_private *const sp = netdev_priv(dev);
1116 + struct phy_device *phydev = NULL;
1117 +
1118 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1119 + phydev = phy_find_first(sp->mii_bus);
1120 + if (!phydev) {
1121 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1122 + return -1;
1123 + }
1124 +
1125 + /* now we are supposed to have a proper phydev, to attach to... */
1126 + BUG_ON(phydev->attached_dev);
1127 +
1128 + phydev = phy_connect(dev, phydev_name(phydev), &ar231x_adjust_link,
1129 + PHY_INTERFACE_MODE_MII);
1130 + if (IS_ERR(phydev)) {
1131 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1132 + return PTR_ERR(phydev);
1133 + }
1134 +
1135 + /* mask with MAC supported features */
1136 + linkmode_set_bit_array(phy_10_100_features_array,
1137 + ARRAY_SIZE(phy_10_100_features_array),
1138 + mask);
1139 + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
1140 + linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
1141 + linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
1142 +
1143 + linkmode_and(phydev->supported, phydev->supported, mask);
1144 + linkmode_copy(phydev->advertising, phydev->supported);
1145 +
1146 + sp->phy_dev = phydev;
1147 +
1148 + printk(KERN_INFO "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1149 + dev->name, phydev->drv->name, phydev_name(phydev));
1150 +
1151 + return 0;
1152 +}
1153 +
1154 --- /dev/null
1155 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
1156 @@ -0,0 +1,282 @@
1157 +/*
1158 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1159 + *
1160 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1161 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1162 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
1163 + *
1164 + * Thanks to Atheros for providing hardware and documentation
1165 + * enabling me to write this driver.
1166 + *
1167 + * This program is free software; you can redistribute it and/or modify
1168 + * it under the terms of the GNU General Public License as published by
1169 + * the Free Software Foundation; either version 2 of the License, or
1170 + * (at your option) any later version.
1171 + */
1172 +
1173 +#ifndef _AR2313_H_
1174 +#define _AR2313_H_
1175 +
1176 +#include <linux/interrupt.h>
1177 +#include <generated/autoconf.h>
1178 +#include <linux/bitops.h>
1179 +#include <ath25_platform.h>
1180 +
1181 +/* probe link timer - 5 secs */
1182 +#define LINK_TIMER (5*HZ)
1183 +
1184 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1185 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1186 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1187 +
1188 +#define AR2313_TX_TIMEOUT (HZ/4)
1189 +
1190 +/* Rings */
1191 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1192 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1193 +
1194 +#define AR2313_MBGET 2
1195 +#define AR2313_MBSET 3
1196 +#define AR2313_PCI_RECONFIG 4
1197 +#define AR2313_PCI_DUMP 5
1198 +#define AR2313_TEST_PANIC 6
1199 +#define AR2313_TEST_NULLPTR 7
1200 +#define AR2313_READ_DATA 8
1201 +#define AR2313_WRITE_DATA 9
1202 +#define AR2313_GET_VERSION 10
1203 +#define AR2313_TEST_HANG 11
1204 +#define AR2313_SYNC 12
1205 +
1206 +#define DMA_RX_ERR_CRC BIT(1)
1207 +#define DMA_RX_ERR_DRIB BIT(2)
1208 +#define DMA_RX_ERR_MII BIT(3)
1209 +#define DMA_RX_EV2 BIT(5)
1210 +#define DMA_RX_ERR_COL BIT(6)
1211 +#define DMA_RX_LONG BIT(7)
1212 +#define DMA_RX_LS BIT(8) /* last descriptor */
1213 +#define DMA_RX_FS BIT(9) /* first descriptor */
1214 +#define DMA_RX_MF BIT(10) /* multicast frame */
1215 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1216 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1217 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1218 +#define DMA_RX_ERROR BIT(15) /* error summary */
1219 +#define DMA_RX_LEN_MASK 0x3fff0000
1220 +#define DMA_RX_LEN_SHIFT 16
1221 +#define DMA_RX_FILT BIT(30)
1222 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1223 +
1224 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1225 +#define DMA_RX1_BSIZE_SHIFT 0
1226 +#define DMA_RX1_CHAINED BIT(24)
1227 +#define DMA_RX1_RER BIT(25)
1228 +
1229 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1230 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1231 +#define DMA_TX_COL_MASK 0x78
1232 +#define DMA_TX_COL_SHIFT 3
1233 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1234 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1235 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1236 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1237 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1238 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1239 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1240 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1241 +
1242 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1243 +#define DMA_TX1_BSIZE_SHIFT 0
1244 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1245 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1246 +#define DMA_TX1_FS BIT(29) /* first segment */
1247 +#define DMA_TX1_LS BIT(30) /* last segment */
1248 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1249 +
1250 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1251 +
1252 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1253 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1254 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1255 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1256 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1257 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1258 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1259 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1260 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1261 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1262 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1263 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1264 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1265 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1266 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1267 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1268 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1269 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1270 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1271 +
1272 +#define MII_ADDR_BUSY BIT(0)
1273 +#define MII_ADDR_WRITE BIT(1)
1274 +#define MII_ADDR_REG_SHIFT 6
1275 +#define MII_ADDR_PHY_SHIFT 11
1276 +#define MII_DATA_SHIFT 0
1277 +
1278 +#define FLOW_CONTROL_FCE BIT(1)
1279 +
1280 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1281 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1282 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1283 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1284 +
1285 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1286 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1287 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1288 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1289 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1290 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1291 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1292 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1293 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1294 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1295 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1296 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1297 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1298 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1299 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1300 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1301 +
1302 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1303 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1304 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1305 +
1306 +typedef struct {
1307 + volatile unsigned int status; /* OWN, Device control and status. */
1308 + volatile unsigned int devcs; /* pkt Control bits + Length */
1309 + volatile unsigned int addr; /* Current Address. */
1310 + volatile unsigned int descr; /* Next descriptor in chain. */
1311 +} ar231x_descr_t;
1312 +
1313 +/**
1314 + * New Combo structure for Both Eth0 AND eth1
1315 + *
1316 + * Don't directly access MII related regs since phy chip could be actually
1317 + * connected to another ethernet block.
1318 + */
1319 +typedef struct {
1320 + volatile unsigned int mac_control; /* 0x00 */
1321 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1322 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1323 + volatile unsigned int __mii_addr; /* 0x14 */
1324 + volatile unsigned int __mii_data; /* 0x18 */
1325 + volatile unsigned int flow_control; /* 0x1c */
1326 + volatile unsigned int vlan_tag; /* 0x20 */
1327 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1328 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1329 +} ETHERNET_STRUCT;
1330 +
1331 +typedef struct {
1332 + volatile unsigned int mii_addr;
1333 + volatile unsigned int mii_data;
1334 +} MII;
1335 +
1336 +/********************************************************************
1337 + * Interrupt controller
1338 + ********************************************************************/
1339 +
1340 +typedef struct {
1341 + volatile unsigned int wdog_control; /* 0x08 */
1342 + volatile unsigned int wdog_timer; /* 0x0c */
1343 + volatile unsigned int misc_status; /* 0x10 */
1344 + volatile unsigned int misc_mask; /* 0x14 */
1345 + volatile unsigned int global_status; /* 0x18 */
1346 + volatile unsigned int reserved; /* 0x1c */
1347 + volatile unsigned int reset_control; /* 0x20 */
1348 +} INTERRUPT;
1349 +
1350 +/********************************************************************
1351 + * DMA controller
1352 + ********************************************************************/
1353 +typedef struct {
1354 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1355 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1356 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1357 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1358 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1359 + volatile unsigned int status; /* 0x14 (CSR5) */
1360 + volatile unsigned int control; /* 0x18 (CSR6) */
1361 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1362 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1363 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1364 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1365 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1366 +} DMA;
1367 +
1368 +/**
1369 + * Struct private for the Sibyte.
1370 + *
1371 + * Elements are grouped so variables used by the tx handling goes
1372 + * together, and will go into the same cache lines etc. in order to
1373 + * avoid cache line contention between the rx and tx handling on SMP.
1374 + *
1375 + * Frequently accessed variables are put at the beginning of the
1376 + * struct to help the compiler generate better/shorter code.
1377 + */
1378 +struct ar231x_private {
1379 + struct net_device *dev;
1380 + struct platform_device *pdev;
1381 + int version;
1382 + u32 mb[2];
1383 +
1384 + volatile MII *phy_regs;
1385 + volatile ETHERNET_STRUCT *eth_regs;
1386 + volatile DMA *dma_regs;
1387 + struct ar231x_eth *cfg;
1388 +
1389 + spinlock_t lock; /* Serialise access to device */
1390 +
1391 + /* RX and TX descriptors, must be adjacent */
1392 + ar231x_descr_t *rx_ring;
1393 + ar231x_descr_t *tx_ring;
1394 +
1395 + struct sk_buff **rx_skb;
1396 + struct sk_buff **tx_skb;
1397 +
1398 + /* RX elements */
1399 + u32 rx_skbprd;
1400 + u32 cur_rx;
1401 +
1402 + /* TX elements */
1403 + u32 tx_prd;
1404 + u32 tx_csm;
1405 +
1406 + /* Misc elements */
1407 + char name[48];
1408 + struct {
1409 + u32 address;
1410 + u32 length;
1411 + char *mapping;
1412 + } desc;
1413 +
1414 + unsigned short link; /* 0 - link down, 1 - link up */
1415 + unsigned short duplex; /* 0 - half, 1 - full */
1416 +
1417 + struct tasklet_struct rx_tasklet;
1418 + int unloading;
1419 +
1420 + struct phy_device *phy_dev;
1421 + struct mii_bus *mii_bus;
1422 +};
1423 +
1424 +/* Prototypes */
1425 +static int ar231x_init(struct net_device *dev);
1426 +#ifdef TX_TIMEOUT
1427 +static void ar231x_tx_timeout(struct net_device *dev);
1428 +#endif
1429 +static int ar231x_restart(struct net_device *dev);
1430 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1431 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1432 +static int ar231x_open(struct net_device *dev);
1433 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1434 +static int ar231x_close(struct net_device *dev);
1435 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
1436 +static void ar231x_init_cleanup(struct net_device *dev);
1437 +
1438 +#endif /* _AR2313_H_ */
1439 --- a/arch/mips/ath25/ar2315_regs.h
1440 +++ b/arch/mips/ath25/ar2315_regs.h
1441 @@ -57,6 +57,9 @@
1442 #define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
1443 #define AR2315_PCI_EXT_SIZE 0x40000000
1444
1445 +/* MII registers offset inside Ethernet MMR region */
1446 +#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14)
1447 +
1448 /*
1449 * Configuration registers
1450 */
1451 --- a/arch/mips/ath25/ar5312_regs.h
1452 +++ b/arch/mips/ath25/ar5312_regs.h
1453 @@ -64,6 +64,10 @@
1454 #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1455 #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1456
1457 +/* MII registers offset inside Ethernet MMR region */
1458 +#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14)
1459 +#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14)
1460 +
1461 /* Reset/Timer Block Address Map */
1462 #define AR5312_TIMER 0x0000 /* countdown timer */
1463 #define AR5312_RELOAD 0x0004 /* timer reload value */
1464 --- a/arch/mips/ath25/ar2315.c
1465 +++ b/arch/mips/ath25/ar2315.c
1466 @@ -132,6 +132,8 @@ static void ar2315_irq_dispatch(void)
1467
1468 if (pending & CAUSEF_IP3)
1469 do_IRQ(AR2315_IRQ_WLAN0);
1470 + else if (pending & CAUSEF_IP4)
1471 + do_IRQ(AR2315_IRQ_ENET0);
1472 #ifdef CONFIG_PCI_AR2315
1473 else if (pending & CAUSEF_IP5)
1474 do_IRQ(AR2315_IRQ_LCBUS_PCI);
1475 @@ -167,6 +169,29 @@ void __init ar2315_arch_init_irq(void)
1476 ar2315_misc_irq_domain = domain;
1477 }
1478
1479 +static void ar2315_device_reset_set(u32 mask)
1480 +{
1481 + u32 val;
1482 +
1483 + val = ar2315_rst_reg_read(AR2315_RESET);
1484 + ar2315_rst_reg_write(AR2315_RESET, val | mask);
1485 +}
1486 +
1487 +static void ar2315_device_reset_clear(u32 mask)
1488 +{
1489 + u32 val;
1490 +
1491 + val = ar2315_rst_reg_read(AR2315_RESET);
1492 + ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
1493 +}
1494 +
1495 +static struct ar231x_eth ar2315_eth_data = {
1496 + .reset_set = ar2315_device_reset_set,
1497 + .reset_clear = ar2315_device_reset_clear,
1498 + .reset_mac = AR2315_RESET_ENET0,
1499 + .reset_phy = AR2315_RESET_EPHY0,
1500 +};
1501 +
1502 static struct resource ar2315_gpio_res[] = {
1503 {
1504 .name = "ar2315-gpio",
1505 @@ -203,6 +228,11 @@ void __init ar2315_init_devices(void)
1506 ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
1507 platform_device_register(&ar2315_gpio);
1508
1509 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
1510 + ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
1511 + AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
1512 + &ar2315_eth_data);
1513 +
1514 ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
1515 }
1516
1517 --- a/arch/mips/ath25/ar5312.c
1518 +++ b/arch/mips/ath25/ar5312.c
1519 @@ -127,6 +127,10 @@ static void ar5312_irq_dispatch(void)
1520
1521 if (pending & CAUSEF_IP2)
1522 do_IRQ(AR5312_IRQ_WLAN0);
1523 + else if (pending & CAUSEF_IP3)
1524 + do_IRQ(AR5312_IRQ_ENET0);
1525 + else if (pending & CAUSEF_IP4)
1526 + do_IRQ(AR5312_IRQ_ENET1);
1527 else if (pending & CAUSEF_IP5)
1528 do_IRQ(AR5312_IRQ_WLAN1);
1529 else if (pending & CAUSEF_IP6)
1530 @@ -160,6 +164,36 @@ void __init ar5312_arch_init_irq(void)
1531 ar5312_misc_irq_domain = domain;
1532 }
1533
1534 +static void ar5312_device_reset_set(u32 mask)
1535 +{
1536 + u32 val;
1537 +
1538 + val = ar5312_rst_reg_read(AR5312_RESET);
1539 + ar5312_rst_reg_write(AR5312_RESET, val | mask);
1540 +}
1541 +
1542 +static void ar5312_device_reset_clear(u32 mask)
1543 +{
1544 + u32 val;
1545 +
1546 + val = ar5312_rst_reg_read(AR5312_RESET);
1547 + ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
1548 +}
1549 +
1550 +static struct ar231x_eth ar5312_eth0_data = {
1551 + .reset_set = ar5312_device_reset_set,
1552 + .reset_clear = ar5312_device_reset_clear,
1553 + .reset_mac = AR5312_RESET_ENET0,
1554 + .reset_phy = AR5312_RESET_EPHY0,
1555 +};
1556 +
1557 +static struct ar231x_eth ar5312_eth1_data = {
1558 + .reset_set = ar5312_device_reset_set,
1559 + .reset_clear = ar5312_device_reset_clear,
1560 + .reset_mac = AR5312_RESET_ENET1,
1561 + .reset_phy = AR5312_RESET_EPHY1,
1562 +};
1563 +
1564 static struct physmap_flash_data ar5312_flash_data = {
1565 .width = 2,
1566 };
1567 @@ -240,6 +274,7 @@ static void __init ar5312_flash_init(voi
1568 void __init ar5312_init_devices(void)
1569 {
1570 struct ath25_boarddata *config;
1571 + u8 *c;
1572
1573 ar5312_flash_init();
1574
1575 @@ -263,8 +298,30 @@ void __init ar5312_init_devices(void)
1576
1577 platform_device_register(&ar5312_gpio);
1578
1579 + /* Fix up MAC addresses if necessary */
1580 + if (is_broadcast_ether_addr(config->enet0_mac))
1581 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1582 +
1583 + /* If ENET0 and ENET1 have the same mac address,
1584 + * increment the one from ENET1 */
1585 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1586 + c = config->enet1_mac + 5;
1587 + while ((c >= config->enet1_mac) && !(++(*c)))
1588 + c--;
1589 + }
1590 +
1591 switch (ath25_soc) {
1592 case ATH25_SOC_AR5312:
1593 + ar5312_eth0_data.macaddr = config->enet0_mac;
1594 + ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii",
1595 + AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0,
1596 + &ar5312_eth0_data);
1597 +
1598 + ar5312_eth1_data.macaddr = config->enet1_mac;
1599 + ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii",
1600 + AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1,
1601 + &ar5312_eth1_data);
1602 +
1603 if (!ath25_board.radio)
1604 return;
1605
1606 @@ -273,8 +330,18 @@ void __init ar5312_init_devices(void)
1607
1608 ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
1609 break;
1610 + /*
1611 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1612 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1613 + */
1614 case ATH25_SOC_AR2312:
1615 case ATH25_SOC_AR2313:
1616 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1617 + ar5312_eth1_data.macaddr = config->enet0_mac;
1618 + ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii",
1619 + AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1,
1620 + &ar5312_eth1_data);
1621 +
1622 if (!ath25_board.radio)
1623 return;
1624 break;
1625 --- a/arch/mips/ath25/devices.h
1626 +++ b/arch/mips/ath25/devices.h
1627 @@ -33,6 +33,8 @@ extern struct ar231x_board_config ath25_
1628 extern void (*ath25_irq_dispatch)(void);
1629
1630 int ath25_find_config(phys_addr_t offset, unsigned long size);
1631 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
1632 + int irq, void *pdata);
1633 void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
1634 int ath25_add_wmac(int nr, u32 base, int irq);
1635
1636 --- a/arch/mips/ath25/devices.c
1637 +++ b/arch/mips/ath25/devices.c
1638 @@ -13,6 +13,51 @@
1639 struct ar231x_board_config ath25_board;
1640 enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
1641
1642 +static struct resource ath25_eth0_res[] = {
1643 + {
1644 + .name = "eth0_membase",
1645 + .flags = IORESOURCE_MEM,
1646 + },
1647 + {
1648 + .name = "eth0_mii",
1649 + .flags = IORESOURCE_MEM,
1650 + },
1651 + {
1652 + .name = "eth0_irq",
1653 + .flags = IORESOURCE_IRQ,
1654 + }
1655 +};
1656 +
1657 +static struct resource ath25_eth1_res[] = {
1658 + {
1659 + .name = "eth1_membase",
1660 + .flags = IORESOURCE_MEM,
1661 + },
1662 + {
1663 + .name = "eth1_mii",
1664 + .flags = IORESOURCE_MEM,
1665 + },
1666 + {
1667 + .name = "eth1_irq",
1668 + .flags = IORESOURCE_IRQ,
1669 + }
1670 +};
1671 +
1672 +static struct platform_device ath25_eth[] = {
1673 + {
1674 + .id = 0,
1675 + .name = "ar231x-eth",
1676 + .resource = ath25_eth0_res,
1677 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
1678 + },
1679 + {
1680 + .id = 1,
1681 + .name = "ar231x-eth",
1682 + .resource = ath25_eth1_res,
1683 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
1684 + }
1685 +};
1686 +
1687 static struct resource ath25_wmac0_res[] = {
1688 {
1689 .name = "wmac0_membase",
1690 @@ -71,6 +116,25 @@ const char *get_system_type(void)
1691 return soc_type_strings[ath25_soc];
1692 }
1693
1694 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
1695 + u32 mii_base, int irq, void *pdata)
1696 +{
1697 + struct resource *res;
1698 +
1699 + ath25_eth[nr].dev.platform_data = pdata;
1700 + res = &ath25_eth[nr].resource[0];
1701 + res->start = base;
1702 + res->end = base + 0x2000 - 1;
1703 + res++;
1704 + res->name = mii_name;
1705 + res->start = mii_base;
1706 + res->end = mii_base + 8 - 1;
1707 + res++;
1708 + res->start = irq;
1709 + res->end = irq;
1710 + return platform_device_register(&ath25_eth[nr]);
1711 +}
1712 +
1713 void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
1714 {
1715 #ifdef CONFIG_SERIAL_8250_CONSOLE
1716 --- a/arch/mips/include/asm/mach-ath25/ath25_platform.h
1717 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
1718 @@ -71,4 +71,15 @@ struct ar231x_board_config {
1719 const char *radio;
1720 };
1721
1722 +/*
1723 + * Platform device information for the Ethernet MAC
1724 + */
1725 +struct ar231x_eth {
1726 + void (*reset_set)(u32);
1727 + void (*reset_clear)(u32);
1728 + u32 reset_mac;
1729 + u32 reset_phy;
1730 + char *macaddr;
1731 +};
1732 +
1733 #endif /* __ASM_MACH_ATH25_PLATFORM_H */
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