target/linux/at91/patches-5.15/102-clk-at91-clk-master-add-register-definition-for-sama.patch

   1 From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Mon, 11 Oct 2021 14:27:08 +0300
   4 Subject: [PATCH 237/247] clk: at91: clk-master: add register definition for
   5  sama7g5's master clock
   6
   7 SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the
   8 register at offset 0x30 (relative to PMC). In the last/first phase of
   9 suspend/resume procedure (which is architecture specific) the parent
  10 of master clocks are changed (via assembly code) for more power saving
  11 (see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable
  12 and at91_mckx_ps_restore). Thus the macros corresponding to register
  13 at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S.
  14 commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's
  15 master clock") introduced the proper macros but didn't adapted the
  16 clk-master.c as well. Thus, this commit adapt the clk-master.c to use
  17 the macros introduced in commit ec03f18cc222 ("clk: at91: add register
  18 definition for sama7g5's master clock").
  19
  20 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  21 Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com
  22 Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  23 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  24 ---
  25  drivers/clk/at91/clk-master.c | 50 ++++++++++++++++-------------------
  26  1 file changed, 23 insertions(+), 27 deletions(-)
  27
  28 --- a/drivers/clk/at91/clk-master.c
  29 +++ b/drivers/clk/at91/clk-master.c
  30 @@ -17,15 +17,7 @@
  31  #define MASTER_DIV_SHIFT       8
  32  #define MASTER_DIV_MASK                0x7
  33
  34 -#define PMC_MCR                        0x30
  35 -#define PMC_MCR_ID_MSK         GENMASK(3, 0)
  36 -#define PMC_MCR_CMD            BIT(7)
  37 -#define PMC_MCR_DIV            GENMASK(10, 8)
  38 -#define PMC_MCR_CSS            GENMASK(20, 16)
  39  #define PMC_MCR_CSS_SHIFT      (16)
  40 -#define PMC_MCR_EN             BIT(28)
  41 -
  42 -#define PMC_MCR_ID(x)          ((x) & PMC_MCR_ID_MSK)
  43
  44  #define MASTER_MAX_ID          4
  45
  46 @@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struc
  47  {
  48         unsigned long flags;
  49         unsigned int val, cparent;
  50 -       unsigned int enable = status ? PMC_MCR_EN : 0;
  51 +       unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
  52
  53         spin_lock_irqsave(master->lock, flags);
  54
  55 -       regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));
  56 -       regmap_read(master->regmap, PMC_MCR, &val);
  57 -       regmap_update_bits(master->regmap, PMC_MCR,
  58 -                          enable | PMC_MCR_CSS | PMC_MCR_DIV |
  59 -                          PMC_MCR_CMD | PMC_MCR_ID_MSK,
  60 +       regmap_write(master->regmap, AT91_PMC_MCR_V2,
  61 +                    AT91_PMC_MCR_V2_ID(master->id));
  62 +       regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
  63 +       regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
  64 +                          enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
  65 +                          AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
  66                            enable | (master->parent << PMC_MCR_CSS_SHIFT) |
  67                            (master->div << MASTER_DIV_SHIFT) |
  68 -                          PMC_MCR_CMD | PMC_MCR_ID(master->id));
  69 +                          AT91_PMC_MCR_V2_CMD |
  70 +                          AT91_PMC_MCR_V2_ID(master->id));
  71
  72 -       cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
  73 +       cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
  74
  75         /* Wait here only if parent is being changed. */
  76         while ((cparent != master->parent) && !clk_master_ready(master))
  77 @@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(s
  78
  79         spin_lock_irqsave(master->lock, flags);
  80
  81 -       regmap_write(master->regmap, PMC_MCR, master->id);
  82 -       regmap_update_bits(master->regmap, PMC_MCR,
  83 -                          PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
  84 -                          PMC_MCR_CMD | PMC_MCR_ID(master->id));
  85 +       regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
  86 +       regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
  87 +                          AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD |
  88 +                          AT91_PMC_MCR_V2_ID_MSK,
  89 +                          AT91_PMC_MCR_V2_CMD |
  90 +                          AT91_PMC_MCR_V2_ID(master->id));
  91
  92         spin_unlock_irqrestore(master->lock, flags);
  93  }
  94 @@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled
  95
  96         spin_lock_irqsave(master->lock, flags);
  97
  98 -       regmap_write(master->regmap, PMC_MCR, master->id);
  99 -       regmap_read(master->regmap, PMC_MCR, &val);
 100 +       regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
 101 +       regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
 102
 103         spin_unlock_irqrestore(master->lock, flags);
 104
 105 -       return !!(val & PMC_MCR_EN);
 106 +       return !!(val & AT91_PMC_MCR_V2_EN);
 107  }
 108
 109  static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
 110 @@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct
 111         master->mux_table = mux_table;
 112
 113         spin_lock_irqsave(master->lock, flags);
 114 -       regmap_write(master->regmap, PMC_MCR, master->id);
 115 -       regmap_read(master->regmap, PMC_MCR, &val);
 116 -       master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
 117 -       master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT;
 118 +       regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
 119 +       regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
 120 +       master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
 121 +       master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;
 122         spin_unlock_irqrestore(master->lock, flags);
 123
 124         hw = &master->hw;