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ar71xx: ag71xx: increase calculated max frame length value
[openwrt/staging/stintel.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define ETH_SWITCH_HEADER_LEN 2
32
33 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
34 {
35 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
36 }
37
38 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
39 {
40 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
41 ag->dev->name,
42 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
43 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
44 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
45
46 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
51 }
52
53 static void ag71xx_dump_regs(struct ag71xx *ag)
54 {
55 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
58 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
59 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
60 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
61 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
62 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
63 ag->dev->name,
64 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
65 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
66 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
67 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
68 ag->dev->name,
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
70 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
71 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
72 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
73 ag->dev->name,
74 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
75 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
77 }
78
79 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
80 {
81 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
82 ag->dev->name, label, intr,
83 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
84 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
85 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
86 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
87 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
88 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
89 }
90
91 static void ag71xx_ring_free(struct ag71xx_ring *ring)
92 {
93 kfree(ring->buf);
94
95 if (ring->descs_cpu)
96 dma_free_coherent(NULL, ring->size * ring->desc_size,
97 ring->descs_cpu, ring->descs_dma);
98 }
99
100 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
101 {
102 int err;
103 int i;
104
105 ring->desc_size = sizeof(struct ag71xx_desc);
106 if (ring->desc_size % cache_line_size()) {
107 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
108 ring, ring->desc_size,
109 roundup(ring->desc_size, cache_line_size()));
110 ring->desc_size = roundup(ring->desc_size, cache_line_size());
111 }
112
113 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
114 &ring->descs_dma, GFP_ATOMIC);
115 if (!ring->descs_cpu) {
116 err = -ENOMEM;
117 goto err;
118 }
119
120
121 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
122 if (!ring->buf) {
123 err = -ENOMEM;
124 goto err;
125 }
126
127 for (i = 0; i < ring->size; i++) {
128 int idx = i * ring->desc_size;
129 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
130 DBG("ag71xx: ring %p, desc %d at %p\n",
131 ring, i, ring->buf[i].desc);
132 }
133
134 return 0;
135
136 err:
137 return err;
138 }
139
140 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
141 {
142 struct ag71xx_ring *ring = &ag->tx_ring;
143 struct net_device *dev = ag->dev;
144 u32 bytes_compl = 0, pkts_compl = 0;
145
146 while (ring->curr != ring->dirty) {
147 u32 i = ring->dirty % ring->size;
148
149 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
150 ring->buf[i].desc->ctrl = 0;
151 dev->stats.tx_errors++;
152 }
153
154 if (ring->buf[i].skb) {
155 bytes_compl += ring->buf[i].len;
156 pkts_compl++;
157 dev_kfree_skb_any(ring->buf[i].skb);
158 }
159 ring->buf[i].skb = NULL;
160 ring->dirty++;
161 }
162
163 /* flush descriptors */
164 wmb();
165
166 netdev_completed_queue(dev, pkts_compl, bytes_compl);
167 }
168
169 static void ag71xx_ring_tx_init(struct ag71xx *ag)
170 {
171 struct ag71xx_ring *ring = &ag->tx_ring;
172 int i;
173
174 for (i = 0; i < ring->size; i++) {
175 ring->buf[i].desc->next = (u32) (ring->descs_dma +
176 ring->desc_size * ((i + 1) % ring->size));
177
178 ring->buf[i].desc->ctrl = DESC_EMPTY;
179 ring->buf[i].skb = NULL;
180 }
181
182 /* flush descriptors */
183 wmb();
184
185 ring->curr = 0;
186 ring->dirty = 0;
187 netdev_reset_queue(ag->dev);
188 }
189
190 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
191 {
192 struct ag71xx_ring *ring = &ag->rx_ring;
193 int i;
194
195 if (!ring->buf)
196 return;
197
198 for (i = 0; i < ring->size; i++)
199 if (ring->buf[i].rx_buf) {
200 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
201 ag->rx_buf_size, DMA_FROM_DEVICE);
202 kfree(ring->buf[i].rx_buf);
203 }
204 }
205
206 static int ag71xx_buffer_offset(struct ag71xx *ag)
207 {
208 int offset = NET_SKB_PAD;
209
210 /*
211 * On AR71xx/AR91xx packets must be 4-byte aligned.
212 *
213 * When using builtin AR8216 support, hardware adds a 2-byte header,
214 * so we don't need any extra alignment in that case.
215 */
216 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
217 return offset;
218
219 return offset + NET_IP_ALIGN;
220 }
221
222 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
223 int offset)
224 {
225 void *data;
226
227 data = kmalloc(ag->rx_buf_size +
228 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
229 GFP_ATOMIC);
230 if (!data)
231 return false;
232
233 buf->rx_buf = data;
234 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
235 DMA_FROM_DEVICE);
236 buf->desc->data = (u32) buf->dma_addr + offset;
237 return true;
238 }
239
240 static int ag71xx_ring_rx_init(struct ag71xx *ag)
241 {
242 struct ag71xx_ring *ring = &ag->rx_ring;
243 unsigned int i;
244 int ret;
245 int offset = ag71xx_buffer_offset(ag);
246
247 ret = 0;
248 for (i = 0; i < ring->size; i++) {
249 ring->buf[i].desc->next = (u32) (ring->descs_dma +
250 ring->desc_size * ((i + 1) % ring->size));
251
252 DBG("ag71xx: RX desc at %p, next is %08x\n",
253 ring->buf[i].desc,
254 ring->buf[i].desc->next);
255 }
256
257 for (i = 0; i < ring->size; i++) {
258 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
259 ret = -ENOMEM;
260 break;
261 }
262
263 ring->buf[i].desc->ctrl = DESC_EMPTY;
264 }
265
266 /* flush descriptors */
267 wmb();
268
269 ring->curr = 0;
270 ring->dirty = 0;
271
272 return ret;
273 }
274
275 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
276 {
277 struct ag71xx_ring *ring = &ag->rx_ring;
278 unsigned int count;
279 int offset = ag71xx_buffer_offset(ag);
280
281 count = 0;
282 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
283 unsigned int i;
284
285 i = ring->dirty % ring->size;
286
287 if (!ring->buf[i].rx_buf &&
288 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
289 break;
290
291 ring->buf[i].desc->ctrl = DESC_EMPTY;
292 count++;
293 }
294
295 /* flush descriptors */
296 wmb();
297
298 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
299
300 return count;
301 }
302
303 static int ag71xx_rings_init(struct ag71xx *ag)
304 {
305 int ret;
306
307 ret = ag71xx_ring_alloc(&ag->tx_ring);
308 if (ret)
309 return ret;
310
311 ag71xx_ring_tx_init(ag);
312
313 ret = ag71xx_ring_alloc(&ag->rx_ring);
314 if (ret)
315 return ret;
316
317 ret = ag71xx_ring_rx_init(ag);
318 return ret;
319 }
320
321 static void ag71xx_rings_cleanup(struct ag71xx *ag)
322 {
323 ag71xx_ring_rx_clean(ag);
324 ag71xx_ring_free(&ag->rx_ring);
325
326 ag71xx_ring_tx_clean(ag);
327 netdev_reset_queue(ag->dev);
328 ag71xx_ring_free(&ag->tx_ring);
329 }
330
331 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
332 {
333 switch (ag->speed) {
334 case SPEED_1000:
335 return "1000";
336 case SPEED_100:
337 return "100";
338 case SPEED_10:
339 return "10";
340 }
341
342 return "?";
343 }
344
345 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
346 {
347 u32 t;
348
349 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
350 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
351
352 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
353
354 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
355 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
356 }
357
358 static void ag71xx_dma_reset(struct ag71xx *ag)
359 {
360 u32 val;
361 int i;
362
363 ag71xx_dump_dma_regs(ag);
364
365 /* stop RX and TX */
366 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
367 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
368
369 /*
370 * give the hardware some time to really stop all rx/tx activity
371 * clearing the descriptors too early causes random memory corruption
372 */
373 mdelay(1);
374
375 /* clear descriptor addresses */
376 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
377 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
378
379 /* clear pending RX/TX interrupts */
380 for (i = 0; i < 256; i++) {
381 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
382 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
383 }
384
385 /* clear pending errors */
386 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
387 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
388
389 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
390 if (val)
391 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
392 ag->dev->name, val);
393
394 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
395
396 /* mask out reserved bits */
397 val &= ~0xff000000;
398
399 if (val)
400 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
401 ag->dev->name, val);
402
403 ag71xx_dump_dma_regs(ag);
404 }
405
406 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
407 MAC_CFG1_SRX | MAC_CFG1_STX)
408
409 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
410
411 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
412 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
413 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
414 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
415 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
416 FIFO_CFG4_VT)
417
418 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
419 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
420 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
421 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
422 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
423 FIFO_CFG5_17 | FIFO_CFG5_SF)
424
425 static void ag71xx_hw_stop(struct ag71xx *ag)
426 {
427 /* disable all interrupts and stop the rx/tx engine */
428 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
429 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
430 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
431 }
432
433 static void ag71xx_hw_setup(struct ag71xx *ag)
434 {
435 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
436
437 /* setup MAC configuration registers */
438 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
439
440 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
441 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
442
443 /* setup max frame length to zero */
444 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
445
446 /* setup FIFO configuration registers */
447 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
448 if (pdata->is_ar724x) {
449 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
450 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
451 } else {
452 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
454 }
455 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
457 }
458
459 static void ag71xx_hw_init(struct ag71xx *ag)
460 {
461 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
462 u32 reset_mask = pdata->reset_bit;
463
464 ag71xx_hw_stop(ag);
465
466 if (pdata->is_ar724x) {
467 u32 reset_phy = reset_mask;
468
469 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
470 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
471
472 ath79_device_reset_set(reset_phy);
473 mdelay(50);
474 ath79_device_reset_clear(reset_phy);
475 mdelay(200);
476 }
477
478 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
479 udelay(20);
480
481 ath79_device_reset_set(reset_mask);
482 mdelay(100);
483 ath79_device_reset_clear(reset_mask);
484 mdelay(200);
485
486 ag71xx_hw_setup(ag);
487
488 ag71xx_dma_reset(ag);
489 }
490
491 static void ag71xx_fast_reset(struct ag71xx *ag)
492 {
493 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
494 struct net_device *dev = ag->dev;
495 u32 reset_mask = pdata->reset_bit;
496 u32 rx_ds, tx_ds;
497 u32 mii_reg;
498
499 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
500
501 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
502 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
503 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
504
505 ath79_device_reset_set(reset_mask);
506 udelay(10);
507 ath79_device_reset_clear(reset_mask);
508 udelay(10);
509
510 ag71xx_dma_reset(ag);
511 ag71xx_hw_setup(ag);
512
513 /* setup max frame length */
514 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
515 ag71xx_max_frame_len(ag->dev->mtu));
516
517 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
518 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
519 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
520
521 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
522 }
523
524 static void ag71xx_hw_start(struct ag71xx *ag)
525 {
526 /* start RX engine */
527 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
528
529 /* enable interrupts */
530 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
531 }
532
533 void ag71xx_link_adjust(struct ag71xx *ag)
534 {
535 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
536 u32 cfg2;
537 u32 ifctl;
538 u32 fifo5;
539
540 if (!ag->link) {
541 ag71xx_hw_stop(ag);
542 netif_carrier_off(ag->dev);
543 if (netif_msg_link(ag))
544 pr_info("%s: link down\n", ag->dev->name);
545 return;
546 }
547
548 if (pdata->is_ar724x)
549 ag71xx_fast_reset(ag);
550
551 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
552 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
553 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
554
555 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
556 ifctl &= ~(MAC_IFCTL_SPEED);
557
558 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
559 fifo5 &= ~FIFO_CFG5_BM;
560
561 switch (ag->speed) {
562 case SPEED_1000:
563 cfg2 |= MAC_CFG2_IF_1000;
564 fifo5 |= FIFO_CFG5_BM;
565 break;
566 case SPEED_100:
567 cfg2 |= MAC_CFG2_IF_10_100;
568 ifctl |= MAC_IFCTL_SPEED;
569 break;
570 case SPEED_10:
571 cfg2 |= MAC_CFG2_IF_10_100;
572 break;
573 default:
574 BUG();
575 return;
576 }
577
578 if (pdata->is_ar91xx)
579 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
580 else if (pdata->is_ar724x)
581 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
582 else
583 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
584
585 if (pdata->set_speed)
586 pdata->set_speed(ag->speed);
587
588 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
589 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
590 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
591 ag71xx_hw_start(ag);
592
593 netif_carrier_on(ag->dev);
594 if (netif_msg_link(ag))
595 pr_info("%s: link up (%sMbps/%s duplex)\n",
596 ag->dev->name,
597 ag71xx_speed_str(ag),
598 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
599
600 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
601 ag->dev->name,
602 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
603 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
604 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
605
606 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
607 ag->dev->name,
608 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
609 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
610 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
611
612 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
613 ag->dev->name,
614 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
615 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
616 }
617
618 static int ag71xx_open(struct net_device *dev)
619 {
620 struct ag71xx *ag = netdev_priv(dev);
621 unsigned int max_frame_len;
622 int ret;
623
624 max_frame_len = ag71xx_max_frame_len(dev->mtu);
625 ag->rx_buf_size = max_frame_len + NET_SKB_PAD + NET_IP_ALIGN;
626
627 /* setup max frame length */
628 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
629
630 ret = ag71xx_rings_init(ag);
631 if (ret)
632 goto err;
633
634 napi_enable(&ag->napi);
635
636 netif_carrier_off(dev);
637 ag71xx_phy_start(ag);
638
639 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
640 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
641
642 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
643
644 netif_start_queue(dev);
645
646 return 0;
647
648 err:
649 ag71xx_rings_cleanup(ag);
650 return ret;
651 }
652
653 static int ag71xx_stop(struct net_device *dev)
654 {
655 struct ag71xx *ag = netdev_priv(dev);
656 unsigned long flags;
657
658 netif_carrier_off(dev);
659 ag71xx_phy_stop(ag);
660
661 spin_lock_irqsave(&ag->lock, flags);
662
663 netif_stop_queue(dev);
664
665 ag71xx_hw_stop(ag);
666 ag71xx_dma_reset(ag);
667
668 napi_disable(&ag->napi);
669 del_timer_sync(&ag->oom_timer);
670
671 spin_unlock_irqrestore(&ag->lock, flags);
672
673 ag71xx_rings_cleanup(ag);
674
675 return 0;
676 }
677
678 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
679 struct net_device *dev)
680 {
681 struct ag71xx *ag = netdev_priv(dev);
682 struct ag71xx_ring *ring = &ag->tx_ring;
683 struct ag71xx_desc *desc;
684 dma_addr_t dma_addr;
685 int i;
686
687 i = ring->curr % ring->size;
688 desc = ring->buf[i].desc;
689
690 if (!ag71xx_desc_empty(desc))
691 goto err_drop;
692
693 if (ag71xx_has_ar8216(ag))
694 ag71xx_add_ar8216_header(ag, skb);
695
696 if (skb->len <= 0) {
697 DBG("%s: packet len is too small\n", ag->dev->name);
698 goto err_drop;
699 }
700
701 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
702 DMA_TO_DEVICE);
703
704 netdev_sent_queue(dev, skb->len);
705 ring->buf[i].len = skb->len;
706 ring->buf[i].skb = skb;
707 ring->buf[i].timestamp = jiffies;
708
709 /* setup descriptor fields */
710 desc->data = (u32) dma_addr;
711 desc->ctrl = skb->len & ag->desc_pktlen_mask;
712
713 /* flush descriptor */
714 wmb();
715
716 ring->curr++;
717 if (ring->curr == (ring->dirty + ring->size)) {
718 DBG("%s: tx queue full\n", ag->dev->name);
719 netif_stop_queue(dev);
720 }
721
722 DBG("%s: packet injected into TX queue\n", ag->dev->name);
723
724 /* enable TX engine */
725 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
726
727 return NETDEV_TX_OK;
728
729 err_drop:
730 dev->stats.tx_dropped++;
731
732 dev_kfree_skb(skb);
733 return NETDEV_TX_OK;
734 }
735
736 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
737 {
738 struct ag71xx *ag = netdev_priv(dev);
739 int ret;
740
741 switch (cmd) {
742 case SIOCETHTOOL:
743 if (ag->phy_dev == NULL)
744 break;
745
746 spin_lock_irq(&ag->lock);
747 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
748 spin_unlock_irq(&ag->lock);
749 return ret;
750
751 case SIOCSIFHWADDR:
752 if (copy_from_user
753 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
754 return -EFAULT;
755 return 0;
756
757 case SIOCGIFHWADDR:
758 if (copy_to_user
759 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
760 return -EFAULT;
761 return 0;
762
763 case SIOCGMIIPHY:
764 case SIOCGMIIREG:
765 case SIOCSMIIREG:
766 if (ag->phy_dev == NULL)
767 break;
768
769 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
770
771 default:
772 break;
773 }
774
775 return -EOPNOTSUPP;
776 }
777
778 static void ag71xx_oom_timer_handler(unsigned long data)
779 {
780 struct net_device *dev = (struct net_device *) data;
781 struct ag71xx *ag = netdev_priv(dev);
782
783 napi_schedule(&ag->napi);
784 }
785
786 static void ag71xx_tx_timeout(struct net_device *dev)
787 {
788 struct ag71xx *ag = netdev_priv(dev);
789
790 if (netif_msg_tx_err(ag))
791 pr_info("%s: tx timeout\n", ag->dev->name);
792
793 schedule_work(&ag->restart_work);
794 }
795
796 static void ag71xx_restart_work_func(struct work_struct *work)
797 {
798 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
799
800 if (ag71xx_get_pdata(ag)->is_ar724x) {
801 ag->link = 0;
802 ag71xx_link_adjust(ag);
803 return;
804 }
805
806 ag71xx_stop(ag->dev);
807 ag71xx_open(ag->dev);
808 }
809
810 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
811 {
812 u32 rx_sm, tx_sm, rx_fd;
813
814 if (likely(time_before(jiffies, timestamp + HZ/10)))
815 return false;
816
817 if (!netif_carrier_ok(ag->dev))
818 return false;
819
820 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
821 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
822 return true;
823
824 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
825 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
826 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
827 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
828 return true;
829
830 return false;
831 }
832
833 static int ag71xx_tx_packets(struct ag71xx *ag)
834 {
835 struct ag71xx_ring *ring = &ag->tx_ring;
836 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
837 int sent = 0;
838 int bytes_compl = 0;
839
840 DBG("%s: processing TX ring\n", ag->dev->name);
841
842 while (ring->dirty != ring->curr) {
843 unsigned int i = ring->dirty % ring->size;
844 struct ag71xx_desc *desc = ring->buf[i].desc;
845 struct sk_buff *skb = ring->buf[i].skb;
846 int len = ring->buf[i].len;
847
848 if (!ag71xx_desc_empty(desc)) {
849 if (pdata->is_ar7240 &&
850 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
851 schedule_work(&ag->restart_work);
852 break;
853 }
854
855 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
856
857 bytes_compl += len;
858 ag->dev->stats.tx_bytes += len;
859 ag->dev->stats.tx_packets++;
860
861 dev_kfree_skb_any(skb);
862 ring->buf[i].skb = NULL;
863
864 ring->dirty++;
865 sent++;
866 }
867
868 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
869
870 if (!sent)
871 return 0;
872
873 netdev_completed_queue(ag->dev, sent, bytes_compl);
874 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
875 netif_wake_queue(ag->dev);
876
877 return sent;
878 }
879
880 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
881 {
882 struct net_device *dev = ag->dev;
883 struct ag71xx_ring *ring = &ag->rx_ring;
884 int offset = ag71xx_buffer_offset(ag);
885 unsigned int pktlen_mask = ag->desc_pktlen_mask;
886 int done = 0;
887
888 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
889 dev->name, limit, ring->curr, ring->dirty);
890
891 while (done < limit) {
892 unsigned int i = ring->curr % ring->size;
893 struct ag71xx_desc *desc = ring->buf[i].desc;
894 struct sk_buff *skb;
895 int pktlen;
896 int err = 0;
897
898 if (ag71xx_desc_empty(desc))
899 break;
900
901 if ((ring->dirty + ring->size) == ring->curr) {
902 ag71xx_assert(0);
903 break;
904 }
905
906 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
907
908 pktlen = desc->ctrl & pktlen_mask;
909 pktlen -= ETH_FCS_LEN;
910
911 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
912 ag->rx_buf_size, DMA_FROM_DEVICE);
913
914 dev->stats.rx_packets++;
915 dev->stats.rx_bytes += pktlen;
916
917 skb = build_skb(ring->buf[i].rx_buf, 0);
918 if (!skb) {
919 kfree(ring->buf[i].rx_buf);
920 goto next;
921 }
922
923 skb_reserve(skb, offset);
924 skb_put(skb, pktlen);
925
926 if (ag71xx_has_ar8216(ag))
927 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
928
929 if (err) {
930 dev->stats.rx_dropped++;
931 kfree_skb(skb);
932 } else {
933 skb->dev = dev;
934 skb->ip_summed = CHECKSUM_NONE;
935 skb->protocol = eth_type_trans(skb, dev);
936 netif_receive_skb(skb);
937 }
938
939 next:
940 ring->buf[i].rx_buf = NULL;
941 done++;
942
943 ring->curr++;
944 }
945
946 ag71xx_ring_rx_refill(ag);
947
948 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
949 dev->name, ring->curr, ring->dirty, done);
950
951 return done;
952 }
953
954 static int ag71xx_poll(struct napi_struct *napi, int limit)
955 {
956 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
957 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
958 struct net_device *dev = ag->dev;
959 struct ag71xx_ring *rx_ring;
960 unsigned long flags;
961 u32 status;
962 int tx_done;
963 int rx_done;
964
965 pdata->ddr_flush();
966 tx_done = ag71xx_tx_packets(ag);
967
968 DBG("%s: processing RX ring\n", dev->name);
969 rx_done = ag71xx_rx_packets(ag, limit);
970
971 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
972
973 rx_ring = &ag->rx_ring;
974 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
975 goto oom;
976
977 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
978 if (unlikely(status & RX_STATUS_OF)) {
979 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
980 dev->stats.rx_fifo_errors++;
981
982 /* restart RX */
983 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
984 }
985
986 if (rx_done < limit) {
987 if (status & RX_STATUS_PR)
988 goto more;
989
990 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
991 if (status & TX_STATUS_PS)
992 goto more;
993
994 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
995 dev->name, rx_done, tx_done, limit);
996
997 napi_complete(napi);
998
999 /* enable interrupts */
1000 spin_lock_irqsave(&ag->lock, flags);
1001 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1002 spin_unlock_irqrestore(&ag->lock, flags);
1003 return rx_done;
1004 }
1005
1006 more:
1007 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1008 dev->name, rx_done, tx_done, limit);
1009 return rx_done;
1010
1011 oom:
1012 if (netif_msg_rx_err(ag))
1013 pr_info("%s: out of memory\n", dev->name);
1014
1015 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1016 napi_complete(napi);
1017 return 0;
1018 }
1019
1020 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1021 {
1022 struct net_device *dev = dev_id;
1023 struct ag71xx *ag = netdev_priv(dev);
1024 u32 status;
1025
1026 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1027 ag71xx_dump_intr(ag, "raw", status);
1028
1029 if (unlikely(!status))
1030 return IRQ_NONE;
1031
1032 if (unlikely(status & AG71XX_INT_ERR)) {
1033 if (status & AG71XX_INT_TX_BE) {
1034 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1035 dev_err(&dev->dev, "TX BUS error\n");
1036 }
1037 if (status & AG71XX_INT_RX_BE) {
1038 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1039 dev_err(&dev->dev, "RX BUS error\n");
1040 }
1041 }
1042
1043 if (likely(status & AG71XX_INT_POLL)) {
1044 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1045 DBG("%s: enable polling mode\n", dev->name);
1046 napi_schedule(&ag->napi);
1047 }
1048
1049 ag71xx_debugfs_update_int_stats(ag, status);
1050
1051 return IRQ_HANDLED;
1052 }
1053
1054 #ifdef CONFIG_NET_POLL_CONTROLLER
1055 /*
1056 * Polling 'interrupt' - used by things like netconsole to send skbs
1057 * without having to re-enable interrupts. It's not called while
1058 * the interrupt routine is executing.
1059 */
1060 static void ag71xx_netpoll(struct net_device *dev)
1061 {
1062 disable_irq(dev->irq);
1063 ag71xx_interrupt(dev->irq, dev);
1064 enable_irq(dev->irq);
1065 }
1066 #endif
1067
1068 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1069 {
1070 struct ag71xx *ag = netdev_priv(dev);
1071 unsigned int max_frame_len;
1072
1073 max_frame_len = ag71xx_max_frame_len(new_mtu);
1074 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1075 return -EINVAL;
1076
1077 if (netif_running(dev))
1078 return -EBUSY;
1079
1080 dev->mtu = new_mtu;
1081 return 0;
1082 }
1083
1084 static const struct net_device_ops ag71xx_netdev_ops = {
1085 .ndo_open = ag71xx_open,
1086 .ndo_stop = ag71xx_stop,
1087 .ndo_start_xmit = ag71xx_hard_start_xmit,
1088 .ndo_do_ioctl = ag71xx_do_ioctl,
1089 .ndo_tx_timeout = ag71xx_tx_timeout,
1090 .ndo_change_mtu = ag71xx_change_mtu,
1091 .ndo_set_mac_address = eth_mac_addr,
1092 .ndo_validate_addr = eth_validate_addr,
1093 #ifdef CONFIG_NET_POLL_CONTROLLER
1094 .ndo_poll_controller = ag71xx_netpoll,
1095 #endif
1096 };
1097
1098 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1099 {
1100 switch (mode) {
1101 case PHY_INTERFACE_MODE_MII:
1102 return "MII";
1103 case PHY_INTERFACE_MODE_GMII:
1104 return "GMII";
1105 case PHY_INTERFACE_MODE_RMII:
1106 return "RMII";
1107 case PHY_INTERFACE_MODE_RGMII:
1108 return "RGMII";
1109 case PHY_INTERFACE_MODE_SGMII:
1110 return "SGMII";
1111 default:
1112 break;
1113 }
1114
1115 return "unknown";
1116 }
1117
1118
1119 static int ag71xx_probe(struct platform_device *pdev)
1120 {
1121 struct net_device *dev;
1122 struct resource *res;
1123 struct ag71xx *ag;
1124 struct ag71xx_platform_data *pdata;
1125 int err;
1126
1127 pdata = pdev->dev.platform_data;
1128 if (!pdata) {
1129 dev_err(&pdev->dev, "no platform data specified\n");
1130 err = -ENXIO;
1131 goto err_out;
1132 }
1133
1134 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1135 dev_err(&pdev->dev, "no MII bus device specified\n");
1136 err = -EINVAL;
1137 goto err_out;
1138 }
1139
1140 dev = alloc_etherdev(sizeof(*ag));
1141 if (!dev) {
1142 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1143 err = -ENOMEM;
1144 goto err_out;
1145 }
1146
1147 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1148 return -EINVAL;
1149
1150 SET_NETDEV_DEV(dev, &pdev->dev);
1151
1152 ag = netdev_priv(dev);
1153 ag->pdev = pdev;
1154 ag->dev = dev;
1155 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1156 AG71XX_DEFAULT_MSG_ENABLE);
1157 spin_lock_init(&ag->lock);
1158
1159 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1160 if (!res) {
1161 dev_err(&pdev->dev, "no mac_base resource found\n");
1162 err = -ENXIO;
1163 goto err_out;
1164 }
1165
1166 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1167 if (!ag->mac_base) {
1168 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1169 err = -ENOMEM;
1170 goto err_free_dev;
1171 }
1172
1173 dev->irq = platform_get_irq(pdev, 0);
1174 err = request_irq(dev->irq, ag71xx_interrupt,
1175 IRQF_DISABLED,
1176 dev->name, dev);
1177 if (err) {
1178 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1179 goto err_unmap_base;
1180 }
1181
1182 dev->base_addr = (unsigned long)ag->mac_base;
1183 dev->netdev_ops = &ag71xx_netdev_ops;
1184 dev->ethtool_ops = &ag71xx_ethtool_ops;
1185
1186 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1187
1188 init_timer(&ag->oom_timer);
1189 ag->oom_timer.data = (unsigned long) dev;
1190 ag->oom_timer.function = ag71xx_oom_timer_handler;
1191
1192 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1193 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1194
1195 ag->max_frame_len = pdata->max_frame_len;
1196 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1197
1198 ag->stop_desc = dma_alloc_coherent(NULL,
1199 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1200
1201 if (!ag->stop_desc)
1202 goto err_free_irq;
1203
1204 ag->stop_desc->data = 0;
1205 ag->stop_desc->ctrl = 0;
1206 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1207
1208 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1209
1210 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1211
1212 ag71xx_dump_regs(ag);
1213
1214 ag71xx_hw_init(ag);
1215
1216 ag71xx_dump_regs(ag);
1217
1218 err = ag71xx_phy_connect(ag);
1219 if (err)
1220 goto err_free_desc;
1221
1222 err = ag71xx_debugfs_init(ag);
1223 if (err)
1224 goto err_phy_disconnect;
1225
1226 platform_set_drvdata(pdev, dev);
1227
1228 err = register_netdev(dev);
1229 if (err) {
1230 dev_err(&pdev->dev, "unable to register net device\n");
1231 goto err_debugfs_exit;
1232 }
1233
1234 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1235 dev->name, dev->base_addr, dev->irq,
1236 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1237
1238 return 0;
1239
1240 err_debugfs_exit:
1241 ag71xx_debugfs_exit(ag);
1242 err_phy_disconnect:
1243 ag71xx_phy_disconnect(ag);
1244 err_free_desc:
1245 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1246 ag->stop_desc_dma);
1247 err_free_irq:
1248 free_irq(dev->irq, dev);
1249 err_unmap_base:
1250 iounmap(ag->mac_base);
1251 err_free_dev:
1252 kfree(dev);
1253 err_out:
1254 platform_set_drvdata(pdev, NULL);
1255 return err;
1256 }
1257
1258 static int ag71xx_remove(struct platform_device *pdev)
1259 {
1260 struct net_device *dev = platform_get_drvdata(pdev);
1261
1262 if (dev) {
1263 struct ag71xx *ag = netdev_priv(dev);
1264
1265 ag71xx_debugfs_exit(ag);
1266 ag71xx_phy_disconnect(ag);
1267 unregister_netdev(dev);
1268 free_irq(dev->irq, dev);
1269 iounmap(ag->mac_base);
1270 kfree(dev);
1271 platform_set_drvdata(pdev, NULL);
1272 }
1273
1274 return 0;
1275 }
1276
1277 static struct platform_driver ag71xx_driver = {
1278 .probe = ag71xx_probe,
1279 .remove = ag71xx_remove,
1280 .driver = {
1281 .name = AG71XX_DRV_NAME,
1282 }
1283 };
1284
1285 static int __init ag71xx_module_init(void)
1286 {
1287 int ret;
1288
1289 ret = ag71xx_debugfs_root_init();
1290 if (ret)
1291 goto err_out;
1292
1293 ret = ag71xx_mdio_driver_init();
1294 if (ret)
1295 goto err_debugfs_exit;
1296
1297 ret = platform_driver_register(&ag71xx_driver);
1298 if (ret)
1299 goto err_mdio_exit;
1300
1301 return 0;
1302
1303 err_mdio_exit:
1304 ag71xx_mdio_driver_exit();
1305 err_debugfs_exit:
1306 ag71xx_debugfs_root_exit();
1307 err_out:
1308 return ret;
1309 }
1310
1311 static void __exit ag71xx_module_exit(void)
1312 {
1313 platform_driver_unregister(&ag71xx_driver);
1314 ag71xx_mdio_driver_exit();
1315 ag71xx_debugfs_root_exit();
1316 }
1317
1318 module_init(ag71xx_module_init);
1319 module_exit(ag71xx_module_exit);
1320
1321 MODULE_VERSION(AG71XX_DRV_VERSION);
1322 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1323 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1324 MODULE_LICENSE("GPL v2");
1325 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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