ar71xx: add v3.18 support
[openwrt/staging/stintel.git] / target / linux / ar71xx / files / drivers / net / dsa / mv88e6063.c
1 /*
2 * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips
3 * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
4 *
5 * This driver was base on: net/dsa/mv88e6060.c
6 * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips
7 * Copyright (c) 2008-2009 Marvell Semiconductor
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15 #include <linux/version.h>
16 #include <linux/list.h>
17 #include <linux/netdevice.h>
18 #include <linux/phy.h>
19 #include <net/dsa.h>
20
21 #define REG_BASE 0x10
22 #define REG_PHY(p) (REG_BASE + (p))
23 #define REG_PORT(p) (REG_BASE + 8 + (p))
24 #define REG_GLOBAL (REG_BASE + 0x0f)
25 #define NUM_PORTS 7
26
27 static int reg_read(struct dsa_switch *ds, int addr, int reg)
28 {
29 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
30 return mdiobus_read(ds->master_mii_bus, addr, reg);
31 #else
32 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
33 return mdiobus_read(bus, addr, reg);
34 #endif
35 }
36
37 #define REG_READ(addr, reg) \
38 ({ \
39 int __ret; \
40 \
41 __ret = reg_read(ds, addr, reg); \
42 if (__ret < 0) \
43 return __ret; \
44 __ret; \
45 })
46
47
48 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
49 {
50 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
51 return mdiobus_write(ds->master_mii_bus, addr, reg, val);
52 #else
53 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
54 return mdiobus_write(bus, addr, reg, val);
55 #endif
56 }
57
58 #define REG_WRITE(addr, reg, val) \
59 ({ \
60 int __ret; \
61 \
62 __ret = reg_write(ds, addr, reg, val); \
63 if (__ret < 0) \
64 return __ret; \
65 })
66
67 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
68 static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr)
69 #else
70 static char *mv88e6063_probe(struct device *host_dev, int sw_addr)
71 #endif
72 {
73 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
74 int ret;
75
76 ret = mdiobus_read(bus, REG_PORT(0), 0x03);
77 if (ret >= 0) {
78 ret &= 0xfff0;
79 if (ret == 0x1530)
80 return "Marvell 88E6063";
81 }
82
83 return NULL;
84 }
85
86 static int mv88e6063_switch_reset(struct dsa_switch *ds)
87 {
88 int i;
89 int ret;
90
91 /*
92 * Set all ports to the disabled state.
93 */
94 for (i = 0; i < NUM_PORTS; i++) {
95 ret = REG_READ(REG_PORT(i), 0x04);
96 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
97 }
98
99 /*
100 * Wait for transmit queues to drain.
101 */
102 msleep(2);
103
104 /*
105 * Reset the switch.
106 */
107 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
108
109 /*
110 * Wait up to one second for reset to complete.
111 */
112 for (i = 0; i < 1000; i++) {
113 ret = REG_READ(REG_GLOBAL, 0x00);
114 if ((ret & 0x8000) == 0x0000)
115 break;
116
117 msleep(1);
118 }
119 if (i == 1000)
120 return -ETIMEDOUT;
121
122 return 0;
123 }
124
125 static int mv88e6063_setup_global(struct dsa_switch *ds)
126 {
127 /*
128 * Disable discarding of frames with excessive collisions,
129 * set the maximum frame size to 1536 bytes, and mask all
130 * interrupt sources.
131 */
132 REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
133
134 /*
135 * Enable automatic address learning, set the address
136 * database size to 1024 entries, and set the default aging
137 * time to 5 minutes.
138 */
139 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
140
141 return 0;
142 }
143
144 static int mv88e6063_setup_port(struct dsa_switch *ds, int p)
145 {
146 int addr = REG_PORT(p);
147
148 /*
149 * Do not force flow control, disable Ingress and Egress
150 * Header tagging, disable VLAN tunneling, and set the port
151 * state to Forwarding. Additionally, if this is the CPU
152 * port, enable Ingress and Egress Trailer tagging mode.
153 */
154 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
155
156 /*
157 * Port based VLAN map: give each port its own address
158 * database, allow the CPU port to talk to each of the 'real'
159 * ports, and allow each of the 'real' ports to only talk to
160 * the CPU port.
161 */
162 REG_WRITE(addr, 0x06,
163 ((p & 0xf) << 12) |
164 (dsa_is_cpu_port(ds, p) ?
165 ds->phys_port_mask :
166 (1 << ds->dst->cpu_port)));
167
168 /*
169 * Port Association Vector: when learning source addresses
170 * of packets, add the address to the address database using
171 * a port bitmap that has only the bit for this port set and
172 * the other bits clear.
173 */
174 REG_WRITE(addr, 0x0b, 1 << p);
175
176 return 0;
177 }
178
179 static int mv88e6063_setup(struct dsa_switch *ds)
180 {
181 int i;
182 int ret;
183
184 ret = mv88e6063_switch_reset(ds);
185 if (ret < 0)
186 return ret;
187
188 /* @@@ initialise atu */
189
190 ret = mv88e6063_setup_global(ds);
191 if (ret < 0)
192 return ret;
193
194 for (i = 0; i < NUM_PORTS; i++) {
195 ret = mv88e6063_setup_port(ds, i);
196 if (ret < 0)
197 return ret;
198 }
199
200 return 0;
201 }
202
203 static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr)
204 {
205 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
206 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
207 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
208
209 return 0;
210 }
211
212 static int mv88e6063_port_to_phy_addr(int port)
213 {
214 if (port >= 0 && port <= NUM_PORTS)
215 return REG_PHY(port);
216 return -1;
217 }
218
219 static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum)
220 {
221 int addr;
222
223 addr = mv88e6063_port_to_phy_addr(port);
224 if (addr == -1)
225 return 0xffff;
226
227 return reg_read(ds, addr, regnum);
228 }
229
230 static int
231 mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
232 {
233 int addr;
234
235 addr = mv88e6063_port_to_phy_addr(port);
236 if (addr == -1)
237 return 0xffff;
238
239 return reg_write(ds, addr, regnum, val);
240 }
241
242 static void mv88e6063_poll_link(struct dsa_switch *ds)
243 {
244 int i;
245
246 for (i = 0; i < DSA_MAX_PORTS; i++) {
247 struct net_device *dev;
248 int uninitialized_var(port_status);
249 int link;
250 int speed;
251 int duplex;
252 int fc;
253
254 dev = ds->ports[i];
255 if (dev == NULL)
256 continue;
257
258 link = 0;
259 if (dev->flags & IFF_UP) {
260 port_status = reg_read(ds, REG_PORT(i), 0x00);
261 if (port_status < 0)
262 continue;
263
264 link = !!(port_status & 0x1000);
265 }
266
267 if (!link) {
268 if (netif_carrier_ok(dev)) {
269 printk(KERN_INFO "%s: link down\n", dev->name);
270 netif_carrier_off(dev);
271 }
272 continue;
273 }
274
275 speed = (port_status & 0x0100) ? 100 : 10;
276 duplex = (port_status & 0x0200) ? 1 : 0;
277 fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
278
279 if (!netif_carrier_ok(dev)) {
280 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
281 "flow control %sabled\n", dev->name,
282 speed, duplex ? "full" : "half",
283 fc ? "en" : "dis");
284 netif_carrier_on(dev);
285 }
286 }
287 }
288
289 static struct dsa_switch_driver mv88e6063_switch_driver = {
290 .tag_protocol = htons(ETH_P_TRAILER),
291 .probe = mv88e6063_probe,
292 .setup = mv88e6063_setup,
293 .set_addr = mv88e6063_set_addr,
294 .phy_read = mv88e6063_phy_read,
295 .phy_write = mv88e6063_phy_write,
296 .poll_link = mv88e6063_poll_link,
297 };
298
299 static int __init mv88e6063_init(void)
300 {
301 register_switch_driver(&mv88e6063_switch_driver);
302 return 0;
303 }
304 module_init(mv88e6063_init);
305
306 static void __exit mv88e6063_cleanup(void)
307 {
308 unregister_switch_driver(&mv88e6063_switch_driver);
309 }
310 module_exit(mv88e6063_cleanup);