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ar71xx: ar934x_nfc: experimental NAND Flash Controller driver for AR934x
[openwrt/staging/stintel.git] / target / linux / ar71xx / files / drivers / mtd / nand / ar934x_nfc.c
1 /*
2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
21
22 #include <linux/platform/ar934x_nfc.h>
23
24 #define AR934X_NFC_REG_CMD 0x00
25 #define AR934X_NFC_REG_CTRL 0x04
26 #define AR934X_NFC_REG_STATUS 0x08
27 #define AR934X_NFC_REG_INT_MASK 0x0c
28 #define AR934X_NFC_REG_INT_STATUS 0x10
29 #define AR934X_NFC_REG_ECC_CTRL 0x14
30 #define AR934X_NFC_REG_ECC_OFFSET 0x18
31 #define AR934X_NFC_REG_ADDR0_0 0x1c
32 #define AR934X_NFC_REG_ADDR0_1 0x24
33 #define AR934X_NFC_REG_ADDR1_0 0x20
34 #define AR934X_NFC_REG_ADDR1_1 0x28
35 #define AR934X_NFC_REG_SPARE_SIZE 0x30
36 #define AR934X_NFC_REG_PROTECT 0x38
37 #define AR934X_NFC_REG_LOOKUP_EN 0x40
38 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
39 #define AR934X_NFC_REG_DMA_ADDR 0x64
40 #define AR934X_NFC_REG_DMA_COUNT 0x68
41 #define AR934X_NFC_REG_DMA_CTRL 0x6c
42 #define AR934X_NFC_REG_MEM_CTRL 0x80
43 #define AR934X_NFC_REG_DATA_SIZE 0x84
44 #define AR934X_NFC_REG_READ_STATUS 0x88
45 #define AR934X_NFC_REG_TIME_SEQ 0x8c
46 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
47 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
48 #define AR934X_NFC_REG_FIFO_DATA 0x98
49 #define AR934X_NFC_REG_TIME_MODE 0x9c
50 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
51 #define AR934X_NFC_REG_FIFO_INIT 0xb0
52 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
53
54 #define AR934X_NFC_CMD_CMD_SEQ_S 0
55 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
56 #define AR934X_NFC_CMD_SEQ_1C 0x00
57 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
58 #define AR934X_NFC_CMD_SEQ_12 0x0c
59 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
60 #define AR934X_NFC_CMD_SEQ_S 0x24
61 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
62 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
63 #define AR934X_NFC_CMD_SEQ_18 0x32
64 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
65 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
66 #define AR934X_NFC_CMD_ADDR_SEL_0 0
67 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
68 #define AR934X_NFC_CMD_CMD0_S 8
69 #define AR934X_NFC_CMD_CMD0_M 0xff
70 #define AR934X_NFC_CMD_CMD1_S 16
71 #define AR934X_NFC_CMD_CMD1_M 0xff
72 #define AR934X_NFC_CMD_CMD2_S 24
73 #define AR934X_NFC_CMD_CMD2_M 0xff
74
75 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
76 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
77 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
78 #define AR934X_NFC_CTRL_INT_EN BIT(4)
79 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
80 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
81 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
82 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
83 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
86 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
87 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
88 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
89 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
90 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
91 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
92 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
93 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
94 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
95 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
96 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
97 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
98 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
99 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
100 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
101 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
102 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
103 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
104 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
105 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
106 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
107
108 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
109 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
110 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
111 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
112 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
113 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
114 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
115 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
119 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
120 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
121
122 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
123 #define AR934X_NFC_INT_CMD_END BIT(1)
124
125 /* default timing values */
126 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
127 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
128 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
129
130 #define AR934X_NFC_ID_BUF_SIZE 8
131 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
132 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
133 #define AR934X_NFC_DONE_TIMEOUT 1000
134
135 #define AR934X_NFC_USE_IRQ true
136 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
137
138 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
139
140 #undef AR934X_NFC_DEBUG_DATA
141 #undef AR934X_NFC_DEBUG
142
143 struct ar934x_nfc;
144
145 static inline __attribute__ ((format (printf, 2, 3)))
146 void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
147 {
148 }
149
150 #ifdef AR934X_NFC_DEBUG
151 #define nfc_dbg(_nfc, fmt, ...) \
152 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
153 #else
154 #define nfc_dbg(_nfc, fmt, ...) \
155 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
156 #endif /* AR934X_NFC_DEBUG */
157
158 #ifdef AR934X_NFC_DEBUG_DATA
159 static void
160 nfc_debug_data(const char *label, void *data, int len)
161 {
162 print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
163 data, len, 0);
164 }
165 #else
166 static inline void
167 nfc_debug_data(const char *label, void *data, int len) {}
168 #endif /* AR934X_NFC_DEBUG_DATA */
169
170 struct ar934x_nfc {
171 struct mtd_info mtd;
172 struct nand_chip nand_chip;
173 struct device *parent;
174 void __iomem *base;
175 void (*select_chip)(int chip_no);
176 int irq;
177 wait_queue_head_t irq_waitq;
178
179 bool spurious_irq_expected;
180 u32 irq_status;
181
182 u32 ctrl_reg;
183 bool small_page;
184 unsigned int addr_count0;
185 unsigned int addr_count1;
186
187 u8 *buf;
188 dma_addr_t buf_dma;
189 unsigned int buf_size;
190 int buf_index;
191
192 int erase1_page_addr;
193
194 int rndout_page_addr;
195 int rndout_read_cmd;
196
197 int seqin_page_addr;
198 int seqin_column;
199 int seqin_read_cmd;
200 };
201
202 static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
203
204 static inline void
205 ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
206 {
207 __raw_writel(val, nfc->base + reg);
208 }
209
210 static inline u32
211 ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
212 {
213 return __raw_readl(nfc->base + reg);
214 }
215
216 static inline struct ar934x_nfc_platform_data *
217 ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc)
218 {
219 return nfc->parent->platform_data;
220 }
221
222 static inline struct
223 ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
224 {
225 return container_of(mtd, struct ar934x_nfc, mtd);
226 }
227
228 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
229 {
230 return AR934X_NFC_USE_IRQ;
231 }
232
233 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
234 {
235 wmb();
236
237 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
238 /* flush write */
239 ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
240 }
241
242 static bool
243 __ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
244 {
245 u32 status;
246
247 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
248 return (status & 0xff) == 0xff;
249 }
250
251 static inline bool
252 __ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
253 {
254 u32 status;
255
256 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
257 return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
258 }
259
260 static int
261 ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
262 {
263 unsigned long timeout;
264
265 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
266 do {
267 if (__ar934x_nfc_dev_ready(nfc))
268 return 0;
269 } while time_before(jiffies, timeout);
270
271 nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
272 ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
273 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
274 return -ETIMEDOUT;
275 }
276
277 static int
278 ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
279 {
280 unsigned long timeout;
281
282 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
283 do {
284 if (__ar934x_nfc_is_dma_ready(nfc))
285 return 0;
286 } while time_before(jiffies, timeout);
287
288 nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
289 ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
290 return -ETIMEDOUT;
291 }
292
293 static int
294 ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
295 {
296 long timeout;
297 int ret;
298
299 timeout = wait_event_timeout(nfc->irq_waitq,
300 (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
301 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
302
303 ret = 0;
304 if (!timeout) {
305 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
306 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
307 /* flush write */
308 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
309
310 nfc_dbg(nfc,
311 "timeout waiting for interrupt, status:%08x\n",
312 nfc->irq_status);
313 ret = -ETIMEDOUT;
314 }
315
316 nfc->irq_status = 0;
317 return ret;
318 }
319
320 static int
321 ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
322 {
323 int ret;
324
325 if (ar934x_nfc_use_irq(nfc))
326 ret = ar934x_nfc_wait_irq(nfc);
327 else
328 ret = ar934x_nfc_wait_dev_ready(nfc);
329
330 if (ret)
331 return ret;
332
333 return ar934x_nfc_wait_dma_ready(nfc);
334 }
335
336 static int
337 ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
338 {
339 nfc->buf = dma_alloc_coherent(nfc->parent, size,
340 &nfc->buf_dma, GFP_KERNEL);
341 if (nfc->buf == NULL) {
342 dev_err(nfc->parent, "no memory for DMA buffer\n");
343 return -ENOMEM;
344 }
345
346 nfc->buf_size = size;
347 nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
348
349 return 0;
350 }
351
352 static void
353 ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
354 {
355 dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
356 }
357
358 static void
359 ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr,
360 u32 *addr0, u32 *addr1)
361 {
362 u32 a0, a1;
363
364 a0 = 0;
365 a1 = 0;
366
367 if (column == -1) {
368 /* ERASE1 */
369 a0 = (page_addr & 0xffff) << 16;
370 a1 = (page_addr >> 16) & 0xf;
371 } else if (page_addr != -1) {
372 /* SEQIN, READ0, etc.. */
373
374 /* TODO: handle 16bit bus width */
375 if (nfc->small_page) {
376 a0 = column & 0xff;
377 a0 |= (page_addr & 0xff) << 8;
378 a0 |= ((page_addr >> 8) & 0xff) << 16;
379 a0 |= ((page_addr >> 16) & 0xff) << 24;
380 } else {
381 a0 = column & 0x0FFF;
382 a0 |= (page_addr & 0xffff) << 16;
383
384 if (nfc->addr_count0 > 4)
385 a1 = (page_addr >> 16) & 0xf;
386 }
387 }
388
389 *addr0 = a0;
390 *addr1 = a1;
391 }
392
393 static void
394 ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
395 {
396 u32 cmd_reg;
397
398 cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
399 AR934X_NFC_CMD_SEQ_1C;
400 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
401
402 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
403 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
404
405 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
406 ar934x_nfc_wait_dev_ready(nfc);
407 }
408
409 static void
410 ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr,
411 int len, u32 cmd_reg, u32 ctrl_reg, bool write)
412 {
413 u32 addr0, addr1;
414 u32 dma_ctrl;
415 int dir;
416 int err;
417 int retries = 0;
418
419 WARN_ON(len & 3);
420
421 if (WARN_ON(len > nfc->buf_size))
422 dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size);
423
424 if (write) {
425 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
426 dir = DMA_TO_DEVICE;
427 } else {
428 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
429 dir = DMA_FROM_DEVICE;
430 }
431
432 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
433
434 dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
435 (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
436 AR934X_NFC_DMA_CTRL_DMA_BURST_S);
437
438 cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
439 ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
440
441 nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
442 (write) ? "write" : "read",
443 addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
444
445 retry:
446 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
447 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
448 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
449 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
450 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
451 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
452 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
453 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
454
455 if (ar934x_nfc_use_irq(nfc)) {
456 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK);
457 /* flush write */
458 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
459 }
460
461 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
462 err = ar934x_nfc_wait_done(nfc);
463 if (err) {
464 dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
465 (write) ? "write" : "read", page_addr);
466
467 ar934x_nfc_restart(nfc);
468 if (retries++ < 5)
469 goto retry;
470
471 dev_err(nfc->parent, "%s operation failed on page %d\n",
472 (write) ? "write" : "read", page_addr);
473 }
474 }
475
476 static void
477 ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
478 {
479 u32 cmd_reg;
480
481 nfc_dbg(nfc, "readid, cmd:%02x\n", command);
482
483 cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
484 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
485
486 ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE, cmd_reg,
487 nfc->ctrl_reg, false);
488
489 nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
490 }
491
492 static void
493 ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column,
494 int page_addr, int len, bool oob)
495 {
496 u32 cmd_reg;
497
498 nfc_dbg(nfc, "read, column=%d page=%d len=%d oob:%d\n",
499 column, page_addr, len, oob);
500
501 cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
502
503 if (nfc->small_page) {
504 cmd_reg |= AR934X_NFC_CMD_SEQ_18;
505 } else {
506 cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
507 cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
508 }
509
510 ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
511 cmd_reg, nfc->ctrl_reg, false);
512
513 nfc_debug_data("[data] ", nfc->buf, len);
514 }
515
516 static void
517 ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column,
518 int page_addr)
519 {
520 u32 addr0, addr1;
521 u32 ctrl_reg;
522 u32 cmd_reg;
523
524 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
525
526 ctrl_reg = nfc->ctrl_reg;
527 if (nfc->small_page) {
528 /* override number of address cycles for the erase command */
529 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
530 AR934X_NFC_CTRL_ADDR_CYCLE0_S);
531 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
532 AR934X_NFC_CTRL_ADDR_CYCLE1_S);
533 ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
534 ctrl_reg |= (nfc->addr_count0 + 1) <<
535 AR934X_NFC_CTRL_ADDR_CYCLE0_S;
536 }
537
538 cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
539 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
540 cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
541
542 nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
543 page_addr, addr0, addr1, cmd_reg, ctrl_reg);
544
545 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
546 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
547 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
548 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
549
550 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
551 ar934x_nfc_wait_dev_ready(nfc);
552 }
553
554 static void
555 ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column,
556 int page_addr, int len)
557 {
558 u32 cmd_reg;
559
560 nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
561 column, page_addr, len);
562
563 nfc_debug_data("[data] ", nfc->buf, len);
564
565 cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
566 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
567 cmd_reg |= AR934X_NFC_CMD_SEQ_12;
568
569 ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
570 cmd_reg, nfc->ctrl_reg, true);
571 }
572
573 static void
574 ar934x_nfc_read_status(struct ar934x_nfc *nfc)
575 {
576 u32 cmd_reg;
577 u32 status;
578
579 cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
580 cmd_reg |= AR934X_NFC_CMD_SEQ_S;
581
582 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
583 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
584
585 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
586 ar934x_nfc_wait_dev_ready(nfc);
587
588 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
589
590 nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
591 cmd_reg, (status & 0xff));
592
593 nfc->buf[0 ^ 3] = status;
594 }
595
596 static void
597 ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
598 int page_addr)
599 {
600 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
601
602 if (command != NAND_CMD_PAGEPROG)
603 nfc->buf_index = 0;
604
605 switch (command) {
606 case NAND_CMD_RESET:
607 ar934x_nfc_send_cmd(nfc, command);
608 break;
609
610 case NAND_CMD_READID:
611 ar934x_nfc_send_readid(nfc, command);
612 break;
613
614 case NAND_CMD_READ0:
615 case NAND_CMD_READ1:
616 if (nfc->small_page)
617 ar934x_nfc_send_read(nfc, command, column, page_addr,
618 mtd->writesize + mtd->oobsize,
619 false);
620 else
621 ar934x_nfc_send_read(nfc, command, column, page_addr,
622 mtd->writesize, false);
623 nfc->rndout_page_addr = page_addr;
624 nfc->rndout_read_cmd = command;
625 break;
626
627 case NAND_CMD_READOOB:
628 if (nfc->small_page) {
629 ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
630 column, page_addr,
631 mtd->oobsize,
632 true);
633 } else {
634 ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
635 column, page_addr,
636 mtd->writesize + mtd->oobsize,
637 true);
638 nfc->buf_index = mtd->writesize;
639 }
640 break;
641
642 case NAND_CMD_RNDOUT:
643 /* emulate subpage read */
644 ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, column,
645 nfc->rndout_page_addr,
646 mtd->writesize, false);
647 break;
648
649 case NAND_CMD_ERASE1:
650 nfc->erase1_page_addr = page_addr;
651 break;
652
653 case NAND_CMD_ERASE2:
654 ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
655 break;
656
657 case NAND_CMD_STATUS:
658 ar934x_nfc_read_status(nfc);
659 break;
660
661 case NAND_CMD_SEQIN:
662 if (nfc->small_page) {
663 /* output read command */
664 if (column >= mtd->writesize) {
665 column -= mtd->writesize;
666 nfc->seqin_read_cmd = NAND_CMD_READOOB;
667 } else if (column < 256) {
668 nfc->seqin_read_cmd = NAND_CMD_READ0;
669 } else {
670 column -= 256;
671 nfc->seqin_read_cmd = NAND_CMD_READ1;
672 }
673 } else {
674 nfc->seqin_read_cmd = NAND_CMD_READ0;
675 }
676 nfc->seqin_column = column;
677 nfc->seqin_page_addr = page_addr;
678 break;
679
680 case NAND_CMD_PAGEPROG:
681 if (nfc->small_page)
682 ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
683
684 ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
685 nfc->seqin_page_addr,
686 nfc->buf_index);
687 break;
688
689 default:
690 dev_err(nfc->parent,
691 "unsupported command: %x, column:%d page_addr=%d\n",
692 command, column, page_addr);
693 break;
694 }
695 }
696
697 static int
698 ar934x_nfc_dev_ready(struct mtd_info *mtd)
699 {
700 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
701
702 return __ar934x_nfc_dev_ready(nfc);
703 }
704
705 static void
706 ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no)
707 {
708 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
709
710 if (nfc->select_chip)
711 nfc->select_chip(chip_no);
712 }
713
714 static u8
715 ar934x_nfc_read_byte(struct mtd_info *mtd)
716 {
717 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
718 unsigned int buf_index;
719 u8 data;
720
721 WARN_ON(nfc->buf_index >= nfc->buf_size);
722
723 buf_index = nfc->buf_index ^ 3;
724 data = nfc->buf[buf_index];
725 nfc->buf_index++;
726
727 return data;
728 }
729
730 static void
731 ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
732 {
733 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
734 int i;
735
736 WARN_ON(nfc->buf_index + len > nfc->buf_size);
737
738 for (i = 0; i < len; i++) {
739 nfc->buf[nfc->buf_index ^ 3] = buf[i];
740 nfc->buf_index++;
741 }
742 }
743
744 static void
745 ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
746 {
747 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
748 int buf_index;
749 int i;
750
751 WARN_ON(nfc->buf_index + len > nfc->buf_size);
752
753 buf_index = nfc->buf_index;
754
755 for (i = 0; i < len; i++) {
756 buf[i] = nfc->buf[buf_index ^ 3];
757 buf_index++;
758 }
759
760 nfc->buf_index = buf_index;
761 }
762
763 static int
764 ar934x_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
765 {
766 int i;
767
768 for (i = 0; i < len; i++)
769 if (buf[i] != ar934x_nfc_read_byte(mtd))
770 return -EFAULT;
771
772 return 0;
773 }
774
775 static void
776 ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
777 {
778 struct ar934x_nfc_platform_data *pdata;
779
780 pdata = ar934x_nfc_get_platform_data(nfc);
781 if (pdata->hw_reset) {
782 pdata->hw_reset(true);
783 pdata->hw_reset(false);
784 }
785
786 /*
787 * setup timings
788 * TODO: make it configurable via platform data
789 */
790 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
791 AR934X_NFC_TIME_SEQ_DEFAULT);
792 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
793 AR934X_NFC_TIMINGS_ASYN_DEFAULT);
794 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
795 AR934X_NFC_TIMINGS_SYN_DEFAULT);
796
797 /* disable WP on all chips, and select chip 0 */
798 ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
799
800 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
801
802 /* initialize Control register */
803 nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
804 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
805
806 if (nfc->small_page) {
807 /* Setup generic sequence register for small page reads. */
808 ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
809 AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
810 }
811 }
812
813 static void
814 ar934x_nfc_restart(struct ar934x_nfc *nfc)
815 {
816 u32 ctrl_reg;
817
818 if (nfc->select_chip)
819 nfc->select_chip(-1);
820
821 ctrl_reg = nfc->ctrl_reg;
822 ar934x_nfc_hw_init(nfc);
823 nfc->ctrl_reg = ctrl_reg;
824
825 if (nfc->select_chip)
826 nfc->select_chip(0);
827
828 ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
829 }
830
831 static irqreturn_t
832 ar934x_nfc_irq_handler(int irq, void *data)
833 {
834 struct ar934x_nfc *nfc = data;
835 u32 status;
836
837 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
838
839 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
840 /* flush write */
841 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
842
843 status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
844 if (status) {
845 nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
846
847 nfc->irq_status = status;
848 nfc->spurious_irq_expected = true;
849 wake_up(&nfc->irq_waitq);
850 } else {
851 if (nfc->spurious_irq_expected) {
852 nfc->spurious_irq_expected = false;
853 } else {
854 dev_warn(nfc->parent, "spurious interrupt\n");
855 }
856 }
857
858 return IRQ_HANDLED;
859 }
860
861 static int __devinit
862 ar934x_nfc_init_tail(struct mtd_info *mtd)
863 {
864 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
865 struct nand_chip *chip = &nfc->nand_chip;
866 u32 ctrl;
867 u32 t;
868 int err;
869
870 switch (mtd->oobsize) {
871 case 16:
872 case 64:
873 case 128:
874 ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
875 break;
876
877 default:
878 dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
879 mtd->oobsize);
880 return -ENXIO;
881 }
882
883 ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
884
885 switch (mtd->erasesize / mtd->writesize) {
886 case 32:
887 t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
888 break;
889
890 case 64:
891 t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
892 break;
893
894 case 128:
895 t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
896 break;
897
898 case 256:
899 t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
900 break;
901
902 default:
903 dev_err(nfc->parent, "unsupported block size: %u\n",
904 mtd->erasesize / mtd->writesize);
905 return -ENXIO;
906 }
907
908 ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
909
910 switch (mtd->writesize) {
911 case 256:
912 nfc->small_page = 1;
913 t = AR934X_NFC_CTRL_PAGE_SIZE_256;
914 break;
915
916 case 512:
917 nfc->small_page = 1;
918 t = AR934X_NFC_CTRL_PAGE_SIZE_512;
919 break;
920
921 case 1024:
922 t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
923 break;
924
925 case 2048:
926 t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
927 break;
928
929 case 4096:
930 t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
931 break;
932
933 case 8192:
934 t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
935 break;
936
937 case 16384:
938 t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
939 break;
940
941 default:
942 dev_err(nfc->parent, "unsupported write size: %d bytes\n",
943 mtd->writesize);
944 return -ENXIO;
945 }
946
947 ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
948
949 if (nfc->small_page) {
950 ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
951
952 if (chip->chipsize > (32 << 20)) {
953 nfc->addr_count0 = 4;
954 nfc->addr_count1 = 3;
955 } else if (chip->chipsize > (2 << 16)) {
956 nfc->addr_count0 = 3;
957 nfc->addr_count1 = 2;
958 } else {
959 nfc->addr_count0 = 2;
960 nfc->addr_count1 = 1;
961 }
962 } else {
963 if (chip->chipsize > (128 << 20)) {
964 nfc->addr_count0 = 5;
965 nfc->addr_count1 = 3;
966 } else if (chip->chipsize > (8 << 16)) {
967 nfc->addr_count0 = 4;
968 nfc->addr_count1 = 2;
969 } else {
970 nfc->addr_count0 = 3;
971 nfc->addr_count1 = 1;
972 }
973 }
974
975 ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
976 ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
977
978 nfc->ctrl_reg = ctrl;
979 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
980
981 ar934x_nfc_free_buf(nfc);
982 err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
983
984 return err;
985 }
986
987 static int __devinit
988 ar934x_nfc_probe(struct platform_device *pdev)
989 {
990 static const char *part_probes[] = { "cmdlinepart", NULL, };
991 struct ar934x_nfc_platform_data *pdata;
992 struct ar934x_nfc *nfc;
993 struct resource *res;
994 struct mtd_info *mtd;
995 struct nand_chip *nand;
996 struct mtd_part_parser_data ppdata;
997 int ret;
998
999 pdata = pdev->dev.platform_data;
1000 if (pdata == NULL) {
1001 dev_err(&pdev->dev, "no platform data defined\n");
1002 return -EINVAL;
1003 }
1004
1005 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1006 if (!res) {
1007 dev_err(&pdev->dev, "failed to get I/O memory\n");
1008 return -EINVAL;
1009 }
1010
1011 nfc = kzalloc(sizeof(struct ar934x_nfc), GFP_KERNEL);
1012 if (!nfc) {
1013 dev_err(&pdev->dev, "failed to allocate driver data\n");
1014 return -ENOMEM;
1015 }
1016
1017 nfc->base = ioremap(res->start, resource_size(res));
1018 if (nfc->base == NULL) {
1019 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1020 ret = -ENXIO;
1021 goto err_free_nand;
1022 }
1023
1024 nfc->irq = platform_get_irq(pdev, 0);
1025 if (nfc->irq < 0) {
1026 dev_err(&pdev->dev, "no IRQ resource specified\n");
1027 ret = -EINVAL;
1028 goto err_unmap;
1029 }
1030
1031 init_waitqueue_head(&nfc->irq_waitq);
1032 ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, IRQF_DISABLED,
1033 dev_name(&pdev->dev), nfc);
1034 if (ret) {
1035 dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret);
1036 goto err_unmap;
1037 }
1038
1039 nfc->parent = &pdev->dev;
1040 nfc->select_chip = pdata->select_chip;
1041
1042 nand = &nfc->nand_chip;
1043 mtd = &nfc->mtd;
1044
1045 mtd->priv = nand;
1046 mtd->owner = THIS_MODULE;
1047 if (pdata->name)
1048 mtd->name = pdata->name;
1049 else
1050 mtd->name = dev_name(&pdev->dev);
1051
1052 nand->options = NAND_NO_AUTOINCR;
1053 nand->chip_delay = 25;
1054 nand->ecc.mode = NAND_ECC_SOFT;
1055
1056 nand->dev_ready = ar934x_nfc_dev_ready;
1057 nand->cmdfunc = ar934x_nfc_cmdfunc;
1058 nand->read_byte = ar934x_nfc_read_byte;
1059 nand->write_buf = ar934x_nfc_write_buf;
1060 nand->read_buf = ar934x_nfc_read_buf;
1061 nand->verify_buf = ar934x_nfc_verify_buf;
1062 nand->select_chip = ar934x_nfc_select_chip;
1063
1064 ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1065 if (ret)
1066 goto err_free_irq;
1067
1068 platform_set_drvdata(pdev, nfc);
1069
1070 ar934x_nfc_hw_init(nfc);
1071
1072 ret = nand_scan_ident(mtd, 1, NULL);
1073 if (ret) {
1074 dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret);
1075 goto err_free_buf;
1076 }
1077
1078 ret = ar934x_nfc_init_tail(mtd);
1079 if (ret) {
1080 dev_err(&pdev->dev, "init tail failed, err:%d\n", ret);
1081 goto err_free_buf;
1082 }
1083
1084 if (pdata->scan_fixup) {
1085 ret = pdata->scan_fixup(mtd);
1086 if (ret)
1087 goto err_free_buf;
1088 }
1089
1090 ret = nand_scan_tail(mtd);
1091 if (ret) {
1092 dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret);
1093 goto err_free_buf;
1094 }
1095
1096 memset(&ppdata, '\0', sizeof(ppdata));
1097 ret = mtd_device_parse_register(mtd, part_probes, &ppdata,
1098 pdata->parts, pdata->nr_parts);
1099 if (ret) {
1100 dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1101 goto err_free_buf;
1102 }
1103
1104 return 0;
1105
1106 err_free_buf:
1107 ar934x_nfc_free_buf(nfc);
1108 err_free_irq:
1109 free_irq(nfc->irq, nfc);
1110 err_unmap:
1111 iounmap(nfc->base);
1112 err_free_nand:
1113 kfree(nfc);
1114 platform_set_drvdata(pdev, NULL);
1115 return ret;
1116 }
1117
1118 static int __devexit
1119 ar934x_nfc_remove(struct platform_device *pdev)
1120 {
1121 struct ar934x_nfc *nfc;
1122
1123 nfc = platform_get_drvdata(pdev);
1124 if (nfc) {
1125 nand_release(&nfc->mtd);
1126 ar934x_nfc_free_buf(nfc);
1127 free_irq(nfc->irq, nfc);
1128 iounmap(nfc->base);
1129 kfree(nfc);
1130 }
1131
1132 return 0;
1133 }
1134
1135 static struct platform_driver ar934x_nfc_driver = {
1136 .probe = ar934x_nfc_probe,
1137 .remove = __devexit_p(ar934x_nfc_remove),
1138 .driver = {
1139 .name = AR934X_NFC_DRIVER_NAME,
1140 .owner = THIS_MODULE,
1141 },
1142 };
1143
1144 module_platform_driver(ar934x_nfc_driver);
1145
1146 MODULE_LICENSE("GPL v2");
1147 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1148 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1149 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
Staging tree of Stijn Tintel