target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Realtek RTL838X architecture specific IRQ handling
   4  *
   5  * Copyright  (C) 2020 B. Koblitz
   6  * based on the original BSP
   7  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   8  *
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqchip.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/of_address.h>
  17 #include <linux/spinlock.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21 #include <mach-rtl838x.h>
  22
  23 #define icu_r32(reg)                    rtl838x_r32(soc_info.icu_base + reg)
  24 #define icu_w32(val, reg)               rtl838x_w32(val, soc_info.icu_base + reg)
  25 #define icu_w32_mask(clear, set, reg)   rtl838x_w32_mask(clear, set, soc_info.icu_base + reg)
  26
  27 static DEFINE_RAW_SPINLOCK(irq_lock);
  28
  29 extern irqreturn_t c0_compare_interrupt(int irq, void *dev_id);
  30
  31
  32 static void rtl838x_ictl_enable_irq(struct irq_data *i)
  33 {
  34         unsigned long flags;
  35
  36         raw_spin_lock_irqsave(&irq_lock, flags);
  37         icu_w32_mask(0, 1 << i->irq, GIMR);
  38         raw_spin_unlock_irqrestore(&irq_lock, flags);
  39 }
  40
  41 static void rtl838x_ictl_disable_irq(struct irq_data *i)
  42 {
  43         unsigned long flags;
  44
  45         raw_spin_lock_irqsave(&irq_lock, flags);
  46         icu_w32_mask(1 << i->irq, 0, GIMR);
  47         raw_spin_unlock_irqrestore(&irq_lock, flags);
  48 }
  49
  50 static void rtl838x_ictl_eoi_irq(struct irq_data *i)
  51 {
  52         unsigned long flags;
  53
  54         raw_spin_lock_irqsave(&irq_lock, flags);
  55         icu_w32_mask(0, 1 << i->irq, GIMR);
  56         raw_spin_unlock_irqrestore(&irq_lock, flags);
  57 }
  58
  59 static struct irq_chip rtl838x_ictl_irq = {
  60         .name = "RTL83xx",
  61         .irq_enable = rtl838x_ictl_enable_irq,
  62         .irq_disable = rtl838x_ictl_disable_irq,
  63         .irq_ack = rtl838x_ictl_disable_irq,
  64         .irq_mask = rtl838x_ictl_disable_irq,
  65         .irq_unmask = rtl838x_ictl_enable_irq,
  66         .irq_eoi = rtl838x_ictl_eoi_irq,
  67 };
  68
  69 /*
  70  *  RTL8390/80/28 Interrupt Scheme
  71  *
  72  *  Source       IRQ      CPU INT
  73  *  --------   -------    -------
  74  *  UART0          31        IP3
  75  *  UART1          30        IP2
  76  *  TIMER0         29        IP6
  77  *  TIMER1         28        IP2
  78  *  OCPTO          27        IP2
  79  *  HLXTO          26        IP2
  80  *  SLXTO          25        IP2
  81  *  NIC            24        IP5
  82  *  GPIO_ABCD      23        IP5
  83  *  SWCORE         20        IP4
  84  */
  85
  86 asmlinkage void plat_irq_dispatch(void)
  87 {
  88         unsigned int pending, ext_int;
  89
  90         pending =  read_c0_cause();
  91
  92         if (pending & CAUSEF_IP7) {
  93                 c0_compare_interrupt(7, NULL);
  94         } else if (pending & CAUSEF_IP6) {
  95                 do_IRQ(TC0_IRQ);
  96         } else if (pending & CAUSEF_IP5) {
  97                 ext_int = icu_r32(GIMR) & icu_r32(GISR);
  98                 if (ext_int & NIC_IP)
  99                         do_IRQ(NIC_IRQ);
 100                 else if (ext_int & GPIO_ABCD_IP)
 101                         do_IRQ(GPIO_ABCD_IRQ);
 102                 else if ((ext_int & GPIO_EFGH_IP) && (soc_info.family == RTL8328_FAMILY_ID))
 103                         do_IRQ(GPIO_EFGH_IRQ);
 104                 else
 105                         spurious_interrupt();
 106         } else if (pending & CAUSEF_IP4) {
 107                 do_IRQ(SWCORE_IRQ);
 108         } else if (pending & CAUSEF_IP3) {
 109                 do_IRQ(UART0_IRQ);
 110         } else if (pending & CAUSEF_IP2) {
 111                 ext_int = icu_r32(GIMR) & icu_r32(GISR);
 112                 if (ext_int & TC1_IP)
 113                         do_IRQ(TC1_IRQ);
 114                 else if (ext_int & UART1_IP)
 115                         do_IRQ(UART1_IRQ);
 116                 else
 117                         spurious_interrupt();
 118         } else {
 119                 spurious_interrupt();
 120         }
 121 }
 122
 123 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 124 {
 125         irq_set_chip_and_handler(hw, &rtl838x_ictl_irq, handle_level_irq);
 126
 127         return 0;
 128 }
 129
 130 static const struct irq_domain_ops irq_domain_ops = {
 131         .xlate = irq_domain_xlate_onecell,
 132         .map = intc_map,
 133 };
 134
 135 int __init icu_of_init(struct device_node *node, struct device_node *parent)
 136 {
 137         int i;
 138         struct irq_domain *domain;
 139         struct resource res;
 140
 141         pr_info("Found Interrupt controller: %s (%s)\n", node->name, node->full_name);
 142         if (of_address_to_resource(node, 0, &res))
 143                 panic("Failed to get icu memory range");
 144
 145         if (!request_mem_region(res.start, resource_size(&res), res.name))
 146                 pr_err("Failed to request icu memory\n");
 147
 148         soc_info.icu_base = ioremap(res.start, resource_size(&res));
 149         pr_info("ICU Memory: %08x\n", (u32)soc_info.icu_base);
 150
 151         mips_cpu_irq_init();
 152
 153         domain = irq_domain_add_simple(node, 32, 0, &irq_domain_ops, NULL);
 154
 155         /* Setup all external HW irqs */
 156         for (i = 8; i < RTL838X_IRQ_ICTL_NUM; i++) {
 157                 irq_domain_associate(domain, i, i);
 158                 irq_set_chip_and_handler(RTL838X_IRQ_ICTL_BASE + i,
 159                                          &rtl838x_ictl_irq, handle_level_irq);
 160         }
 161
 162         if (request_irq(RTL838X_ICTL1_IRQ, no_action, IRQF_NO_THREAD,
 163                         "IRQ cascade 1", NULL)) {
 164                 pr_err("request_irq() cascade 1 for irq %d failed\n", RTL838X_ICTL1_IRQ);
 165         }
 166         if (request_irq(RTL838X_ICTL2_IRQ, no_action, IRQF_NO_THREAD,
 167                         "IRQ cascade 2", NULL)) {
 168                 pr_err("request_irq() cascade 2 for irq %d failed\n", RTL838X_ICTL2_IRQ);
 169         }
 170         if (request_irq(RTL838X_ICTL3_IRQ, no_action, IRQF_NO_THREAD,
 171                         "IRQ cascade 3", NULL)) {
 172                 pr_err("request_irq() cascade 3 for irq %d failed\n", RTL838X_ICTL3_IRQ);
 173         }
 174         if (request_irq(RTL838X_ICTL4_IRQ, no_action, IRQF_NO_THREAD,
 175                         "IRQ cascade 4", NULL)) {
 176                 pr_err("request_irq() cascade 4 for irq %d failed\n", RTL838X_ICTL4_IRQ);
 177         }
 178         if (request_irq(RTL838X_ICTL5_IRQ, no_action, IRQF_NO_THREAD,
 179                         "IRQ cascade 5", NULL)) {
 180                 pr_err("request_irq() cascade 5 for irq %d failed\n", RTL838X_ICTL5_IRQ);
 181         }
 182
 183         /* Set up interrupt routing scheme */
 184         icu_w32(IRR0_SETTING, IRR0);
 185         if (soc_info.family == RTL8380_FAMILY_ID)
 186                 icu_w32(IRR1_SETTING_RTL838X, IRR1);
 187         else
 188                 icu_w32(IRR1_SETTING_RTL839X, IRR1);
 189         icu_w32(IRR2_SETTING, IRR2);
 190         icu_w32(IRR3_SETTING, IRR3);
 191
 192         /* Enable timer0 and uart0 interrupts */
 193         icu_w32(TC0_IE | UART0_IE, GIMR);
 194         return 0;
 195 }
 196
 197 void __init arch_init_irq(void)
 198 {
 199         /* do board-specific irq initialization */
 200         irqchip_init();
 201 }
 202
 203 IRQCHIP_DECLARE(mips_cpu_intc, "rtl838x,icu", icu_of_init);