target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include <linux/of_mdio.h>
   4 #include <linux/of_platform.h>
   5
   6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
   7 #include "rtl83xx.h"
   8
   9 extern struct rtl83xx_soc_info soc_info;
  10
  11 extern const struct rtl838x_reg rtl838x_reg;
  12 extern const struct rtl838x_reg rtl839x_reg;
  13 extern const struct dsa_switch_ops rtl83xx_switch_ops;
  14
  15 DEFINE_MUTEX(smi_lock);
  16
  17
  18 // TODO: unused
  19 static void dump_fdb(struct rtl838x_switch_priv *priv)
  20 {
  21         struct rtl838x_l2_entry e;
  22         int i;
  23
  24         mutex_lock(&priv->reg_mutex);
  25
  26         for (i = 0; i < priv->fib_entries; i++) {
  27                 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
  28
  29                 if (!e.valid) /* Check for invalid entry */
  30                         continue;
  31
  32                 pr_debug("-> port %02d: mac %pM, vid: %d, rvid: %d, MC: %d, %d\n",
  33                         e.port, &e.mac[0], e.vid, e.rvid, e.is_ip_mc, e.is_ipv6_mc);
  34         }
  35
  36         mutex_unlock(&priv->reg_mutex);
  37 }
  38
  39 // TODO: unused
  40 static void rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
  41 {
  42         u32 cmd, msti = 0;
  43         u32 port_state[4];
  44         int index, bit, i;
  45         int pos = port;
  46         int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
  47
  48         /* CPU PORT can only be configured on RTL838x */
  49         if (port >= priv->cpu_port || port > 51)
  50                 return;
  51
  52         mutex_lock(&priv->reg_mutex);
  53
  54         /* For the RTL839x, the bits are left-aligned in the 128 bit field */
  55         if (priv->family_id == RTL8390_FAMILY_ID)
  56                 pos += 12;
  57
  58         index = n - (pos >> 4) - 1;
  59         bit = (pos << 1) % 32;
  60
  61         if (priv->family_id == RTL8380_FAMILY_ID) {
  62                 cmd = BIT(15) /* Execute cmd */
  63                         | BIT(14) /* Read */
  64                         | 2 << 12 /* Table type 0b10 */
  65                         | (msti & 0xfff);
  66         } else {
  67                 cmd = BIT(16) /* Execute cmd */
  68                         | 0 << 15 /* Read */
  69                         | 5 << 12 /* Table type 0b101 */
  70                         | (msti & 0xfff);
  71         }
  72         priv->r->exec_tbl0_cmd(cmd);
  73
  74         for (i = 0; i < n; i++)
  75                 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
  76
  77         mutex_unlock(&priv->reg_mutex);
  78 }
  79
  80 int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
  81 {
  82         u32 val;
  83         u32 offset = 0;
  84         struct rtl838x_switch_priv *priv = ds->priv;
  85
  86         if (phy_addr >= 24 && phy_addr <= 27
  87                 && priv->ports[24].phy == PHY_RTL838X_SDS) {
  88                 if (phy_addr == 26)
  89                         offset = 0x100;
  90                 val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
  91                 return val;
  92         }
  93
  94         if (soc_info.family == RTL8390_FAMILY_ID)
  95                 rtl839x_read_phy(phy_addr, 0, phy_reg, &val);
  96         else
  97                 rtl838x_read_phy(phy_addr, 0, phy_reg, &val);
  98         return val;
  99 }
 100
 101 int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
 102 {
 103         u32 offset = 0;
 104         struct rtl838x_switch_priv *priv = ds->priv;
 105
 106         if (phy_addr >= 24 && phy_addr <= 27
 107              && priv->ports[24].phy == PHY_RTL838X_SDS) {
 108                 if (phy_addr == 26)
 109                         offset = 0x100;
 110                 sw_w32(val, MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2));
 111                 return 0;
 112         }
 113         if (soc_info.family == RTL8390_FAMILY_ID)
 114                 return rtl839x_write_phy(phy_addr, 0, phy_reg, val);
 115         else
 116                 return rtl838x_write_phy(phy_addr, 0, phy_reg, val);
 117 }
 118
 119 static int rtl83xx_mdio_read(struct mii_bus *bus, int addr, int regnum)
 120 {
 121         int ret;
 122         struct rtl838x_switch_priv *priv = bus->priv;
 123
 124         ret = rtl83xx_dsa_phy_read(priv->ds, addr, regnum);
 125         return ret;
 126 }
 127
 128 static int rtl83xx_mdio_write(struct mii_bus *bus, int addr, int regnum,
 129                                  u16 val)
 130 {
 131         struct rtl838x_switch_priv *priv = bus->priv;
 132
 133         return rtl83xx_dsa_phy_write(priv->ds, addr, regnum, val);
 134 }
 135
 136 static void rtl8380_sds_rst(int mac)
 137 {
 138         u32 offset = (mac == 24) ? 0 : 0x100;
 139
 140         sw_w32_mask(1 << 11, 0, RTL8380_SDS4_FIB_REG0 + offset);
 141         sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
 142         sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
 143         sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
 144         sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
 145         pr_debug("SERDES reset: %d\n", mac);
 146 }
 147
 148 static int __init rtl8380_sds_power(int mac, int val)
 149 {
 150         u32 mode = (val == 1) ? 0x4 : 0x9;
 151         u32 offset = (mac == 24) ? 5 : 0;
 152
 153         if ((mac != 24) && (mac != 26)) {
 154                 pr_err("%s: not a fibre port: %d\n", __func__, mac);
 155                 return -1;
 156         }
 157
 158         sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
 159
 160         rtl8380_sds_rst(mac);
 161
 162         return 0;
 163 }
 164
 165 static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
 166 {
 167         struct device *dev = priv->dev;
 168         struct device_node *dn, *mii_np = dev->of_node;
 169         struct mii_bus *bus;
 170         int ret;
 171         u32 pn;
 172
 173         pr_debug("In %s\n", __func__);
 174         mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
 175         if (mii_np) {
 176                 pr_debug("Found compatible MDIO node!\n");
 177         } else {
 178                 dev_err(priv->dev, "no %s child node found", "mdio-bus");
 179                 return -ENODEV;
 180         }
 181
 182         priv->mii_bus = of_mdio_find_bus(mii_np);
 183         if (!priv->mii_bus) {
 184                 pr_debug("Deferring probe of mdio bus\n");
 185                 return -EPROBE_DEFER;
 186         }
 187         if (!of_device_is_available(mii_np))
 188                 ret = -ENODEV;
 189
 190         bus = devm_mdiobus_alloc(priv->ds->dev);
 191         if (!bus)
 192                 return -ENOMEM;
 193
 194         bus->name = "rtl838x slave mii";
 195         bus->read = &rtl83xx_mdio_read;
 196         bus->write = &rtl83xx_mdio_write;
 197         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
 198         bus->parent = dev;
 199         priv->ds->slave_mii_bus = bus;
 200         priv->ds->slave_mii_bus->priv = priv;
 201
 202         ret = mdiobus_register(priv->ds->slave_mii_bus);
 203         if (ret && mii_np) {
 204                 of_node_put(dn);
 205                 return ret;
 206         }
 207
 208         dn = mii_np;
 209         for_each_node_by_name(dn, "ethernet-phy") {
 210                 if (of_property_read_u32(dn, "reg", &pn))
 211                         continue;
 212
 213                 priv->ports[pn].dp = dsa_to_port(priv->ds, pn);
 214
 215                 // Check for the integrated SerDes of the RTL8380M first
 216                 if (of_property_read_bool(dn, "phy-is-integrated")
 217                         && priv->id == 0x8380 && pn >= 24) {
 218                         pr_debug("----> FÓUND A SERDES\n");
 219                         priv->ports[pn].phy = PHY_RTL838X_SDS;
 220                         continue;
 221                 }
 222
 223                 if (of_property_read_bool(dn, "phy-is-integrated")
 224                         && !of_property_read_bool(dn, "sfp")) {
 225                         priv->ports[pn].phy = PHY_RTL8218B_INT;
 226                         continue;
 227                 }
 228
 229                 if (!of_property_read_bool(dn, "phy-is-integrated")
 230                         && of_property_read_bool(dn, "sfp")) {
 231                         priv->ports[pn].phy = PHY_RTL8214FC;
 232                         continue;
 233                 }
 234
 235                 if (!of_property_read_bool(dn, "phy-is-integrated")
 236                         && !of_property_read_bool(dn, "sfp")) {
 237                         priv->ports[pn].phy = PHY_RTL8218B_EXT;
 238                         continue;
 239                 }
 240         }
 241
 242         /* Disable MAC polling the PHY so that we can start configuration */
 243         priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
 244
 245         /* Enable PHY control via SoC */
 246         if (priv->family_id == RTL8380_FAMILY_ID) {
 247                 /* Enable PHY control via SoC */
 248                 sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
 249         } else {
 250                 /* Disable PHY polling via SoC */
 251                 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
 252         }
 253
 254         /* Power on fibre ports and reset them if necessary */
 255         if (priv->ports[24].phy == PHY_RTL838X_SDS) {
 256                 pr_debug("Powering on fibre ports & reset\n");
 257                 rtl8380_sds_power(24, 1);
 258                 rtl8380_sds_power(26, 1);
 259         }
 260
 261         pr_debug("%s done\n", __func__);
 262         return 0;
 263 }
 264
 265 static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
 266 {
 267         int t = sw_r32(priv->r->l2_ctrl_1);
 268
 269         t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
 270
 271         if (priv->family_id == RTL8380_FAMILY_ID)
 272                 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
 273         else
 274                 t = (t * 3) / 5;
 275
 276         pr_debug("L2 AGING time: %d sec\n", t);
 277         pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
 278         return t;
 279 }
 280
 281 static int __init rtl83xx_sw_probe(struct platform_device *pdev)
 282 {
 283         int err = 0, i;
 284         struct rtl838x_switch_priv *priv;
 285         struct device *dev = &pdev->dev;
 286         u64 irq_mask;
 287
 288         pr_debug("Probing RTL838X switch device\n");
 289         if (!pdev->dev.of_node) {
 290                 dev_err(dev, "No DT found\n");
 291                 return -EINVAL;
 292         }
 293
 294         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 295         if (!priv)
 296                 return -ENOMEM;
 297
 298         priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
 299
 300         if (!priv->ds)
 301                 return -ENOMEM;
 302         priv->ds->dev = dev;
 303         priv->ds->priv = priv;
 304         priv->ds->ops = &rtl83xx_switch_ops;
 305         priv->dev = dev;
 306
 307         priv->family_id = soc_info.family;
 308         priv->id = soc_info.id;
 309         if (soc_info.family == RTL8380_FAMILY_ID) {
 310                 priv->cpu_port = RTL838X_CPU_PORT;
 311                 priv->port_mask = 0x1f;
 312                 priv->r = &rtl838x_reg;
 313                 priv->ds->num_ports = 30;
 314                 priv->fib_entries = 8192;
 315                 rtl8380_get_version(priv);
 316         } else {
 317                 priv->cpu_port = RTL839X_CPU_PORT;
 318                 priv->port_mask = 0x3f;
 319                 priv->r = &rtl839x_reg;
 320                 priv->ds->num_ports = 53;
 321                 priv->fib_entries = 16384;
 322                 rtl8390_get_version(priv);
 323         }
 324         pr_debug("Chip version %c\n", priv->version);
 325
 326         err = rtl83xx_mdio_probe(priv);
 327         if (err) {
 328                 /* Probing fails the 1st time because of missing ethernet driver
 329                  * initialization. Use this to disable traffic in case the bootloader left if on
 330                  */
 331                 return err;
 332         }
 333         err = dsa_register_switch(priv->ds);
 334         if (err) {
 335                 dev_err(dev, "Error registering switch: %d\n", err);
 336                 return err;
 337         }
 338
 339         /* Enable link and media change interrupts. Are the SERDES masks needed? */
 340         sw_w32_mask(0, 3, priv->r->isr_glb_src);
 341         /* ... for all ports */
 342         irq_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x0FFFFFFF : 0xFFFFFFFFFFFFFULL;
 343         priv->r->set_port_reg_le(irq_mask, priv->r->isr_port_link_sts_chg);
 344         priv->r->set_port_reg_le(irq_mask, priv->r->imr_port_link_sts_chg);
 345
 346         priv->link_state_irq = platform_get_irq(pdev, 0);;
 347         if (priv->family_id == RTL8380_FAMILY_ID) {
 348                 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
 349                                 IRQF_SHARED, "rtl838x-link-state", priv->ds);
 350         } else {
 351                 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
 352                                 IRQF_SHARED, "rtl839x-link-state", priv->ds);
 353         }
 354         if (err) {
 355                 dev_err(dev, "Error setting up switch interrupt.\n");
 356                 /* Need to free allocated switch here */
 357         }
 358
 359         /* Enable interrupts for switch */
 360         sw_w32(0x1, priv->r->imr_glb);
 361
 362         rtl83xx_get_l2aging(priv);
 363
 364 /*
 365         if (priv->family_id == RTL8380_FAMILY_ID)
 366                 rtl83xx_storm_control_init(priv);
 367 */
 368
 369         /* Clear all destination ports for mirror groups */
 370         for (i = 0; i < 4; i++)
 371                 priv->mirror_group_ports[i] = -1;
 372
 373         rtl838x_dbgfs_init(priv);
 374
 375         return err;
 376 }
 377
 378 static int rtl83xx_sw_remove(struct platform_device *pdev)
 379 {
 380         // TODO:
 381         pr_debug("Removing platform driver for rtl83xx-sw\n");
 382         return 0;
 383 }
 384
 385 static const struct of_device_id rtl83xx_switch_of_ids[] = {
 386         { .compatible = "realtek,rtl83xx-switch"},
 387         { /* sentinel */ }
 388 };
 389
 390
 391 MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
 392
 393 static struct platform_driver rtl83xx_switch_driver = {
 394         .probe = rtl83xx_sw_probe,
 395         .remove = rtl83xx_sw_remove,
 396         .driver = {
 397                 .name = "rtl83xx-switch",
 398                 .pm = NULL,
 399                 .of_match_table = rtl83xx_switch_of_ids,
 400         },
 401 };
 402
 403 module_platform_driver(rtl83xx_switch_driver);
 404
 405 MODULE_AUTHOR("B. Koblitz");
 406 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
 407 MODULE_LICENSE("GPL");