target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2009 Realtek Semiconductor Corp.
   4  *
   5  * This program is free software: you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation, either version 3 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #ifndef _RTL838X_SPI_H
  18 #define _RTL838X_SPI_H
  19
  20
  21 /*
  22  * Register access macros
  23  */
  24
  25 #define spi_r32(reg)            readl(rtl838x_nor->base + reg)
  26 #define spi_w32(val, reg)       writel(val, rtl838x_nor->base + reg)
  27 #define spi_w32_mask(clear, set, reg)   \
  28         spi_w32((spi_r32(reg) & ~(clear)) | (set), reg)
  29
  30 #define SPI_WAIT_READY          do { \
  31                                 } while (!(spi_r32(SFCSR) & SFCSR_SPI_RDY))
  32
  33 #define spi_w32w(val, reg)      do { \
  34                                         writel(val, rtl838x_nor->base + reg); \
  35                                         SPI_WAIT_READY; \
  36                                 } while (0)
  37
  38 #define SFCR   (0x00)                   /*SPI Flash Configuration Register*/
  39         #define SFCR_CLK_DIV(val)       ((val)<<29)
  40         #define SFCR_EnableRBO          (1<<28)
  41         #define SFCR_EnableWBO          (1<<27)
  42         #define SFCR_SPI_TCS(val)       ((val)<<23) /*4 bit, 1111 */
  43
  44 #define SFCR2  (0x04)   /*For memory mapped I/O */
  45         #define SFCR2_SFCMD(val)        ((val)<<24) /*8 bit, 1111_1111 */
  46         #define SFCR2_SIZE(val)         ((val)<<21) /*3 bit, 111 */
  47         #define SFCR2_RDOPT             (1<<20)
  48         #define SFCR2_CMDIO(val)        ((val)<<18) /*2 bit, 11 */
  49         #define SFCR2_ADDRIO(val)       ((val)<<16) /*2 bit, 11 */
  50         #define SFCR2_DUMMYCYCLE(val)   ((val)<<13) /*3 bit, 111 */
  51         #define SFCR2_DATAIO(val)       ((val)<<11) /*2 bit, 11 */
  52         #define SFCR2_HOLD_TILL_SFDR2   (1<<10)
  53         #define SFCR2_GETSIZE(x)        (((x)&0x00E00000)>>21)
  54
  55 #define SFCSR  (0x08)   /*SPI Flash Control&Status Register*/
  56         #define SFCSR_SPI_CSB0          (1<<31)
  57         #define SFCSR_SPI_CSB1          (1<<30)
  58         #define SFCSR_LEN(val)          ((val)<<28)  /*2 bits*/
  59         #define SFCSR_SPI_RDY           (1<<27)
  60         #define SFCSR_IO_WIDTH(val)     ((val)<<25)  /*2 bits*/
  61         #define SFCSR_CHIP_SEL          (1<<24)
  62         #define SFCSR_CMD_BYTE(val)     ((val)<<16)  /*8 bit, 1111_1111 */
  63
  64 #define SFDR   (0x0C)   /*SPI Flash Data Register*/
  65 #define SFDR2  (0x10)   /*SPI Flash Data Register - for post SPI bootup setting*/
  66         #define SPI_CS_INIT             (SFCSR_SPI_CSB0 | SFCSR_SPI_CSB1 | SPI_LEN1)
  67         #define SPI_CS0                 SFCSR_SPI_CSB0
  68         #define SPI_CS1                 SFCSR_SPI_CSB1
  69         #define SPI_eCS0                ((SFCSR_SPI_CSB1)) /*and SFCSR to active CS0*/
  70         #define SPI_eCS1                ((SFCSR_SPI_CSB0)) /*and SFCSR to active CS1*/
  71
  72         #define SPI_WIP (1)             /* Write In Progress */
  73         #define SPI_WEL (1<<1)          /* Write Enable Latch*/
  74         #define SPI_SST_QIO_WIP (1<<7)  /* SST QIO Flash Write In Progress */
  75         #define SPI_LEN_INIT 0xCFFFFFFF /* and SFCSR to init   */
  76         #define SPI_LEN4    0x30000000  /* or SFCSR to set */
  77         #define SPI_LEN3    0x20000000  /* or SFCSR to set */
  78         #define SPI_LEN2    0x10000000  /* or SFCSR to set */
  79         #define SPI_LEN1    0x00000000  /* or SFCSR to set */
  80         #define SPI_SETLEN(val) do {            \
  81                         SPI_REG(SFCSR) &= 0xCFFFFFFF;   \
  82                         SPI_REG(SFCSR) |= (val-1)<<28;  \
  83                 } while (0)
  84 /*
  85  * SPI interface control
  86  */
  87 #define RTL8390_SOC_SPI_MMIO_CONF (0x04)
  88
  89 #define IOSTATUS_CIO_MASK (0x00000038)
  90
  91 /* Chip select: bits 4-7*/
  92 #define CS0 (1<<4)
  93 #define R_MODE 0x04
  94
  95 /* io_status */
  96 #define IO1 (1<<0)
  97 #define IO2 (1<<1)
  98 #define CIO1 (1<<3)
  99 #define CIO2 (1<<4)
 100 #define CMD_IO1 (1<<6)
 101 #define W_ADDR_IO1 ((1)<<12)
 102 #define R_ADDR_IO2 ((2)<<9)
 103 #define R_DATA_IO2 ((2)<<15)
 104 #define W_DATA_IO1 ((1)<<18)
 105
 106 /* Commands */
 107 #define SPI_C_RSTQIO 0xFF
 108
 109 #define SPI_MAX_TRANSFER_SIZE 256
 110
 111 #endif          /* _RTL838X_SPI_H */