realtek: update the tree to the latest refactored version
[openwrt/staging/rmilecki.git] / target / linux / realtek / dts / rtl838x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 /dts-v1/;
4
5 #define STRINGIZE(s) #s
6 #define LAN_LABEL(p, s) STRINGIZE(p ## s)
7 #define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
8
9 #define INTERNAL_PHY(n) \
10 phy##n: ethernet-phy@##n { \
11 reg = <##n>; \
12 compatible = "ethernet-phy-ieee802.3-c22"; \
13 phy-is-integrated; \
14 };
15
16 #define EXTERNAL_PHY(n) \
17 phy##n: ethernet-phy@##n { \
18 reg = <##n>; \
19 compatible = "ethernet-phy-ieee802.3-c22"; \
20 };
21
22 #define EXTERNAL_SFP_PHY(n) \
23 phy##n: ethernet-phy@##n { \
24 compatible = "ethernet-phy-ieee802.3-c22"; \
25 sfp; \
26 media = "fibre"; \
27 reg = <##n>; \
28 };
29
30 #define SWITCH_PORT(n, s, m) \
31 port@##n { \
32 reg = <##n>; \
33 label = SWITCH_PORT_LABEL(s) ; \
34 phy-handle = <&phy##n>; \
35 phy-mode = #m ; \
36 };
37
38 / {
39 #address-cells = <1>;
40 #size-cells = <1>;
41
42 compatible = "realtek,rtl838x-soc";
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 frequency = <500000000>;
48
49 cpu@0 {
50 compatible = "mips,mips4KEc";
51 reg = <0>;
52 };
53 };
54
55 memory@0 {
56 device_type = "memory";
57 reg = <0x0 0x8000000>;
58 };
59
60 chosen {
61 bootargs = "console=ttyS0,38400";
62 };
63
64 cpuintc: cpuintc {
65 #address-cells = <0>;
66 #interrupt-cells = <1>;
67 interrupt-controller;
68 compatible = "mti,cpu-interrupt-controller";
69 };
70
71 intc: rtlintc {
72 #address-cells = <0>;
73 #interrupt-cells = <1>;
74 interrupt-controller;
75 compatible = "realtek,rt8380-intc";
76 reg = <0xb8003000 0x20>;
77 };
78
79 spi0: spi@b8001200 {
80 status = "okay";
81
82 compatible = "realtek,rtl838x-nor";
83 reg = <0xb8001200 0x100>;
84
85 #address-cells = <1>;
86 #size-cells = <0>;
87 };
88
89 uart0: uart@b8002000 {
90 status = "okay";
91
92 compatible = "ns16550a";
93 reg = <0xb8002000 0x100>;
94
95 clock-frequency = <200000000>;
96
97 interrupt-parent = <&cpuintc>;
98 interrupts = <3>;
99
100 reg-io-width = <1>;
101 reg-shift = <2>;
102 fifo-size = <1>;
103 no-loopback-test;
104 };
105
106 uart1: uart@b8002100 {
107 pinctrl-names = "default";
108 pinctrl-0 = <&enable_uart1>;
109
110 status = "okay";
111
112 compatible = "ns16550a";
113 reg = <0xb8002100 0x100>;
114
115 clock-frequency = <200000000>;
116
117 interrupt-parent = <&intc>;
118 interrupts = <30>;
119
120 reg-io-width = <1>;
121 reg-shift = <2>;
122 fifo-size = <1>;
123 no-loopback-test;
124 };
125
126 gpio0: gpio-controller@b8003500 {
127 compatible = "realtek,rtl838x-gpio";
128 reg = <0xb8003500 0x20>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-parent = <&intc>;
132 interrupts = <23>;
133 };
134
135 gpio1: rtl8231-gpio {
136 status = "disabled";
137 compatible = "realtek,rtl8231-gpio";
138 #gpio-cells = <2>;
139 indirect-access-bus-id = <0>;
140 gpio-controller;
141 };
142
143 pinmux: pinmux@bb001000 {
144 compatible = "pinctrl-single";
145 reg = <0xbb001000 0x4>;
146
147 pinctrl-single,bit-per-mux;
148 pinctrl-single,register-width = <32>;
149 pinctrl-single,function-mask = <0x1>;
150 #pinctrl-cells = <2>;
151
152 enable_uart1: pinmux_enable_uart1 {
153 pinctrl-single,bits = <0x0 0x10 0x10>;
154 };
155 };
156
157 ethernet0: ethernet@bb00a300 {
158 status = "okay";
159
160 compatible = "realtek,rtl838x-eth";
161 reg = <0xbb00a300 0x100>;
162 interrupt-parent = <&intc>;
163 interrupts = <24>;
164 #interrupt-cells = <1>;
165 phy-mode = "internal";
166
167 fixed-link {
168 speed = <1000>;
169 full-duplex;
170 };
171 };
172
173 switch0: switch@bb000000 {
174 status = "okay";
175
176 interrupt-parent = <&cpuintc>;
177 interrupts = <4>;
178
179
180 compatible = "realtek,rtl83xx-switch";
181 };
182 };