target/linux/ramips/patches-5.10/0118-staging-mt7621-pci-phy-re-do-xtal_mode-detection.patch

   1 From ff83e3023cb8fc3b5dfc12e0c91bf1eb9dc4c4c6 Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Sat, 21 Mar 2020 14:36:24 +0100
   4 Subject: [PATCH] staging: mt7621-pci-phy: re-do 'xtal_mode' detection
   5
   6 Detection of the Xtal mode is using magic numbers that
   7 can be avoided using properly some definitions and a more
   8 accurate variable name from 'reg' into 'xtal_mode'. This
   9 increase readability.
  10
  11 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  12 Link: https://lore.kernel.org/r/20200321133624.31388-4-sergio.paracuellos@gmail.com
  13 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  14 ---
  15  drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 15 ++++++++++-----
  16  1 file changed, 10 insertions(+), 5 deletions(-)
  17
  18 --- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
  19 +++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
  20 @@ -75,6 +75,9 @@
  21
  22  #define RG_PE1_FRC_MSTCKDIV                    BIT(5)
  23
  24 +#define XTAL_MODE_SEL_SHIFT                    6
  25 +#define XTAL_MODE_SEL_MASK                     0x7
  26 +
  27  #define MAX_PHYS       2
  28
  29  /**
  30 @@ -136,9 +139,11 @@ static void mt7621_bypass_pipe_rst(struc
  31  static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)
  32  {
  33         struct device *dev = phy->dev;
  34 -       u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
  35 +       u32 xtal_mode;
  36 +
  37 +       xtal_mode = (rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0)
  38 +                    >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
  39
  40 -       reg = (reg >> 6) & 0x7;
  41         /* Set PCIe Port PHY to disable SSC */
  42         /* Debug Xtal Type */
  43         mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG,
  44 @@ -154,13 +159,13 @@ static void mt7621_set_phy_for_ssc(struc
  45                                RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
  46         }
  47
  48 -       if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
  49 +       if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
  50                 /* Set Pre-divider ratio (for host mode) */
  51                 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
  52                                RG_PE1_H_PLL_PREDIV,
  53                                RG_PE1_H_PLL_PREDIV_VAL(0x01));
  54                 dev_info(dev, "Xtal is 40MHz\n");
  55 -       } else if (reg >= 6) { /* 25MHz Xal */
  56 +       } else if (xtal_mode >= 6) { /* 25MHz Xal */
  57                 mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
  58                                RG_PE1_H_PLL_PREDIV,
  59                                RG_PE1_H_PLL_PREDIV_VAL(0x00));
  60 @@ -206,7 +211,7 @@ static void mt7621_set_phy_for_ssc(struc
  61         mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG,
  62                        RG_PE1_H_PLL_BR, RG_PE1_H_PLL_BR_VAL(0x00));
  63
  64 -       if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
  65 +       if (xtal_mode <= 5 && xtal_mode >= 3) { /* 40MHz Xtal */
  66                 /* set force mode enable of da_pe1_mstckdiv */
  67                 mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG,
  68                                RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV,