target/linux/ramips/patches-5.10/0106-staging-mt7621-pci-phy-add-mt7621_phy_rmw-to-simplif.patch

   1 From bf0c6782e5b9a6deee4e223655325dc004fae8dd Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Sun, 15 Mar 2020 17:01:54 +0100
   4 Subject: [PATCH] staging: mt7621-pci-phy: add 'mt7621_phy_rmw' to simplify
   5  code
   6
   7 In order to simplify driver code and decrease a bit LOC add new
   8 function 'mt7621_phy_rmw' where clear and set bits are passed as
   9 arguments.
  10
  11 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  12 Link: https://lore.kernel.org/r/20200315160154.10292-1-sergio.paracuellos@gmail.com
  13 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  14 ---
  15  drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 158 +++++++++++-------------
  16  1 file changed, 71 insertions(+), 87 deletions(-)
  17
  18 --- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
  19 +++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
  20 @@ -120,17 +120,25 @@ static inline void phy_write(struct mt76
  21         regmap_write(phy->regmap, reg, val);
  22  }
  23
  24 +static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy,
  25 +                                 u32 reg, u32 clr, u32 set)
  26 +{
  27 +       u32 val = phy_read(phy, reg);
  28 +
  29 +       val &= ~clr;
  30 +       val |= set;
  31 +       phy_write(phy, val, reg);
  32 +}
  33 +
  34  static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy,
  35                                    struct mt7621_pci_phy_instance *instance)
  36  {
  37         u32 offset = (instance->index != 1) ?
  38                 RG_PE1_PIPE_REG : RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH;
  39 -       u32 reg;
  40
  41 -       reg = phy_read(phy, offset);
  42 -       reg &= ~(RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
  43 -       reg |= (RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
  44 -       phy_write(phy, reg, offset);
  45 +       mt7621_phy_rmw(phy, offset,
  46 +                      RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC,
  47 +                      RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
  48  }
  49
  50  static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy,
  51 @@ -139,97 +147,77 @@ static void mt7621_set_phy_for_ssc(struc
  52         struct device *dev = phy->dev;
  53         u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
  54         u32 offset;
  55 -       u32 val;
  56
  57         reg = (reg >> 6) & 0x7;
  58         /* Set PCIe Port PHY to disable SSC */
  59         /* Debug Xtal Type */
  60 -       val = phy_read(phy, RG_PE1_FRC_H_XTAL_REG);
  61 -       val &= ~(RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE);
  62 -       val |= RG_PE1_FRC_H_XTAL_TYPE;
  63 -       val |= RG_PE1_H_XTAL_TYPE_VAL(0x00);
  64 -       phy_write(phy, val, RG_PE1_FRC_H_XTAL_REG);
  65 +       mt7621_phy_rmw(phy, RG_PE1_FRC_H_XTAL_REG,
  66 +                      RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE,
  67 +                      RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE_VAL(0x00));
  68
  69         /* disable port */
  70         offset = (instance->index != 1) ?
  71                 RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
  72 -       val = phy_read(phy, offset);
  73 -       val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
  74 -       val |= RG_PE1_FRC_PHY_EN;
  75 -       phy_write(phy, val, offset);
  76 -
  77 -       /* Set Pre-divider ratio (for host mode) */
  78 -       val = phy_read(phy, RG_PE1_H_PLL_REG);
  79 -       val &= ~(RG_PE1_H_PLL_PREDIV);
  80 +       mt7621_phy_rmw(phy, offset,
  81 +                      RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
  82
  83         if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
  84 -               val |= RG_PE1_H_PLL_PREDIV_VAL(0x01);
  85 -               phy_write(phy, val, RG_PE1_H_PLL_REG);
  86 +               /* Set Pre-divider ratio (for host mode) */
  87 +               mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
  88 +                              RG_PE1_H_PLL_PREDIV,
  89 +                              RG_PE1_H_PLL_PREDIV_VAL(0x01));
  90                 dev_info(dev, "Xtal is 40MHz\n");
  91 -       } else { /* 25MHz | 20MHz Xtal */
  92 -               val |= RG_PE1_H_PLL_PREDIV_VAL(0x00);
  93 -               phy_write(phy, val, RG_PE1_H_PLL_REG);
  94 -               if (reg >= 6) {
  95 -                       dev_info(dev, "Xtal is 25MHz\n");
  96 -
  97 -                       /* Select feedback clock */
  98 -                       val = phy_read(phy, RG_PE1_H_PLL_FBKSEL_REG);
  99 -                       val &= ~(RG_PE1_H_PLL_FBKSEL);
 100 -                       val |= RG_PE1_H_PLL_FBKSEL_VAL(0x01);
 101 -                       phy_write(phy, val, RG_PE1_H_PLL_FBKSEL_REG);
 102 -
 103 -                       /* DDS NCPO PCW (for host mode) */
 104 -                       val = phy_read(phy, RG_PE1_H_LCDDS_SSC_PRD_REG);
 105 -                       val &= ~(RG_PE1_H_LCDDS_SSC_PRD);
 106 -                       val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000);
 107 -                       phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG);
 108 -
 109 -                       /* DDS SSC dither period control */
 110 -                       val = phy_read(phy, RG_PE1_H_LCDDS_SSC_PRD_REG);
 111 -                       val &= ~(RG_PE1_H_LCDDS_SSC_PRD);
 112 -                       val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d);
 113 -                       phy_write(phy, val, RG_PE1_H_LCDDS_SSC_PRD_REG);
 114 -
 115 -                       /* DDS SSC dither amplitude control */
 116 -                       val = phy_read(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG);
 117 -                       val &= ~(RG_PE1_H_LCDDS_SSC_DELTA |
 118 -                                RG_PE1_H_LCDDS_SSC_DELTA1);
 119 -                       val |= RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a);
 120 -                       val |= RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a);
 121 -                       phy_write(phy, val, RG_PE1_H_LCDDS_SSC_DELTA_REG);
 122 -               } else {
 123 -                       dev_info(dev, "Xtal is 20MHz\n");
 124 -               }
 125 +       } else if (reg >= 6) { /* 25MHz Xal */
 126 +               mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
 127 +                              RG_PE1_H_PLL_PREDIV,
 128 +                              RG_PE1_H_PLL_PREDIV_VAL(0x00));
 129 +               /* Select feedback clock */
 130 +               mt7621_phy_rmw(phy, RG_PE1_H_PLL_FBKSEL_REG,
 131 +                              RG_PE1_H_PLL_FBKSEL,
 132 +                              RG_PE1_H_PLL_FBKSEL_VAL(0x01));
 133 +               /* DDS NCPO PCW (for host mode) */
 134 +               mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
 135 +                              RG_PE1_H_LCDDS_SSC_PRD,
 136 +                              RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000));
 137 +               /* DDS SSC dither period control */
 138 +               mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_PRD_REG,
 139 +                              RG_PE1_H_LCDDS_SSC_PRD,
 140 +                              RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d));
 141 +               /* DDS SSC dither amplitude control */
 142 +               mt7621_phy_rmw(phy, RG_PE1_H_LCDDS_SSC_DELTA_REG,
 143 +                              RG_PE1_H_LCDDS_SSC_DELTA |
 144 +                              RG_PE1_H_LCDDS_SSC_DELTA1,
 145 +                              RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a) |
 146 +                              RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a));
 147 +               dev_info(dev, "Xtal is 25MHz\n");
 148 +       } else { /* 20MHz Xtal */
 149 +               mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
 150 +                              RG_PE1_H_PLL_PREDIV,
 151 +                              RG_PE1_H_PLL_PREDIV_VAL(0x00));
 152 +
 153 +               dev_info(dev, "Xtal is 20MHz\n");
 154         }
 155
 156         /* DDS clock inversion */
 157 -       val = phy_read(phy, RG_PE1_LCDDS_CLK_PH_INV_REG);
 158 -       val &= ~(RG_PE1_LCDDS_CLK_PH_INV);
 159 -       val |= RG_PE1_LCDDS_CLK_PH_INV;
 160 -       phy_write(phy, val, RG_PE1_LCDDS_CLK_PH_INV_REG);
 161 +       mt7621_phy_rmw(phy, RG_PE1_LCDDS_CLK_PH_INV_REG,
 162 +                      RG_PE1_LCDDS_CLK_PH_INV, RG_PE1_LCDDS_CLK_PH_INV);
 163
 164         /* Set PLL bits */
 165 -       val = phy_read(phy, RG_PE1_H_PLL_REG);
 166 -       val &= ~(RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR |
 167 -                RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN);
 168 -       val |= RG_PE1_H_PLL_BC_VAL(0x02);
 169 -       val |= RG_PE1_H_PLL_BP_VAL(0x06);
 170 -       val |= RG_PE1_H_PLL_IR_VAL(0x02);
 171 -       val |= RG_PE1_H_PLL_IC_VAL(0x01);
 172 -       val |= RG_PE1_PLL_DIVEN_VAL(0x02);
 173 -       phy_write(phy, val, RG_PE1_H_PLL_REG);
 174 -
 175 -       val = phy_read(phy, RG_PE1_H_PLL_BR_REG);
 176 -       val &= ~(RG_PE1_H_PLL_BR);
 177 -       val |= RG_PE1_H_PLL_BR_VAL(0x00);
 178 -       phy_write(phy, val, RG_PE1_H_PLL_BR_REG);
 179 +       mt7621_phy_rmw(phy, RG_PE1_H_PLL_REG,
 180 +                      RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR |
 181 +                      RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN,
 182 +                      RG_PE1_H_PLL_BC_VAL(0x02) | RG_PE1_H_PLL_BP_VAL(0x06) |
 183 +                      RG_PE1_H_PLL_IR_VAL(0x02) | RG_PE1_H_PLL_IC_VAL(0x01) |
 184 +                      RG_PE1_PLL_DIVEN_VAL(0x02));
 185 +
 186 +       mt7621_phy_rmw(phy, RG_PE1_H_PLL_BR_REG,
 187 +                      RG_PE1_H_PLL_BR, RG_PE1_H_PLL_BR_VAL(0x00));
 188
 189         if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
 190                 /* set force mode enable of da_pe1_mstckdiv */
 191 -               val = phy_read(phy, RG_PE1_MSTCKDIV_REG);
 192 -               val &= ~(RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV);
 193 -               val |= (RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV);
 194 -               phy_write(phy, val, RG_PE1_MSTCKDIV_REG);
 195 +               mt7621_phy_rmw(phy, RG_PE1_MSTCKDIV_REG,
 196 +                              RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV,
 197 +                              RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV);
 198         }
 199  }
 200
 201 @@ -252,13 +240,11 @@ static int mt7621_pci_phy_power_on(struc
 202         struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
 203         u32 offset = (instance->index != 1) ?
 204                 RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
 205 -       u32 val;
 206
 207         /* Enable PHY and disable force mode */
 208 -       val = phy_read(mphy, offset);
 209 -       val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
 210 -       val |= (RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
 211 -       phy_write(mphy, val, offset);
 212 +       mt7621_phy_rmw(mphy, offset,
 213 +                      RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN,
 214 +                      RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
 215
 216         return 0;
 217  }
 218 @@ -269,13 +255,11 @@ static int mt7621_pci_phy_power_off(stru
 219         struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
 220         u32 offset = (instance->index != 1) ?
 221                 RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
 222 -       u32 val;
 223
 224         /* Disable PHY */
 225 -       val = phy_read(mphy, offset);
 226 -       val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
 227 -       val |= RG_PE1_FRC_PHY_EN;
 228 -       phy_write(mphy, val, offset);
 229 +       mt7621_phy_rmw(mphy, offset,
 230 +                      RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN,
 231 +                      RG_PE1_FRC_PHY_EN);
 232
 233         return 0;
 234  }